OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog/] [F80ToF32.v] - Blame information for rev 16

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 16 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch<remove>@finitron.ca
7
//       ||
8
//
9
//
10
//
11
// This source file is free software: you can redistribute it and/or modify 
12
// it under the terms of the GNU Lesser General Public License as published 
13
// by the Free Software Foundation, either version 3 of the License, or     
14
// (at your option) any later version.                                      
15
//                                                                          
16
// This source file is distributed in the hope that it will be useful,      
17
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
18
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
19
// GNU General Public License for more details.                             
20
//                                                                          
21
// You should have received a copy of the GNU General Public License        
22
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
23
//                                                                          
24
// ============================================================================
25
 
26
module F80ToF32(a, o);
27
input [79:0] a;
28
output [31:0] o;
29
 
30
reg signo;
31
reg [7:0] expo;
32
reg [22:0] mano;
33
 
34
assign o = {signo,expo,mano};
35
 
36
wire signi;
37
wire [14:0] expi;
38
wire [63:0] mani;
39
wire xinf;      // exponent infinite
40
wire vz;        // value zero
41
wire xz;        // exponent zero
42
 
43
fpDecomp #(80) u1 (.i(a), .sgn(signi), .exp(expi), .man(mani), .xinf(xinf), .xz(xz), .vz(vz) );
44
 
45
always @*
46
begin
47
  // sign out always just = sign in
48
  signo = signi;
49
 
50
  // special check for zero
51
  if (vz) begin
52
    expo <= 0;
53
    mano <= 0;
54
  end
55
  // convert infinity / nan
56
  // infinity in = infinity out
57
  else if (xinf) begin
58
    expo <= 8'h7f;
59
    mano <= mani[63:41];
60
  end
61
  // convert denormal
62
  // a denormal was really a number with an exponent of -126
63
  // this value is easily represented in the double format
64
  // it may be possible to normalize the value if it isn't
65
  // zero
66
  else if (xz) begin
67
    expo <= 8'h00;
68
    mano <= 23'h0;
69
  end
70
  // convert typical number
71
  // adjust exponent, copy mantissa
72
  else begin
73
        if (expi < 15'h3fff - 8'h7f) begin
74
                expo <= 8'h00;  // zero
75
                mano <= 23'h0;
76
        end
77
        else if (expi > 15'h3fff + 8'h7f) begin
78
                expo <= 8'hFF;  // Infinity
79
                mano <= 23'h0;
80
        end
81
        else begin
82
        expo <= expi - 15'h3fff + 8'h7f;
83
        mano <= mani[63:41];
84
    end
85
  end
86
end
87
 
88
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.