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`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2014  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
// FT816Float.v
//  - Triple precision floating point accelerator
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// 1600 LUTs 350 FF's
// 140 MHz
// ============================================================================
//
`define SIMULATION      1'b1
 
module FT816Float(rst, clk, vda, rw, ad, db, rdy);
parameter pIOAddress = 24'hFEA200;
parameter pRdyStyle = 1'b1;
parameter EMSB = 15;
parameter FMSB = 79;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
parameter FADD = 8'd1;
parameter FSUB = 8'd2;
parameter FMUL = 8'd3;
parameter FDIV = 8'd4;
parameter FIX2FLT = 8'd5;
parameter FLT2FIX = 8'd6;
parameter FABS = 8'd7;
parameter ABS = 8'd7;
parameter NABS = 8'd8;
parameter FNABS = 8'd8;
parameter MD1 = 8'd10;
parameter ABSSWP = 8'd11;
parameter ABSSWP1 = 8'd12;
parameter NORM1 = 8'd13;
parameter NORM = 8'd14;
parameter ADD = 8'd15;
parameter FCOMPL = 8'd16;
parameter FNEG = 8'd16;
parameter SWAP = 8'd17;
parameter FIXED_ADD = 8'h81;
parameter FIXED_SUB = 8'h82;
parameter FIXED_MUL = 8'h83;
parameter FIXED_DIV = 8'h84;
parameter FIXED_ABS = 8'h87;
parameter FIXED_NEG = 8'h90;
parameter SWPALG = 8'd18;
parameter ADDEND = 8'd19;
parameter ALGNSW = 8'd20;
parameter RTLOG = 8'd22;
parameter FMUL1 = 8'd24;
parameter FMUL2 = 8'd25;
parameter MUL1 = 8'd26;
parameter FMUL3 = 8'd27;
parameter MUL2 = 8'd28;
parameter MDEND = 8'd29;
parameter FDIV1 = 8'd30;
parameter MD2 = 8'd31;
parameter MD3 = 8'd32;
parameter OVCHK = 8'd34;
parameter OVFL = 8'd35;
parameter DIV1 = 8'd36;
parameter IDLE = 8'd62;
parameter RESET = 8'd63;
 
input rst;
input clk;
input vda;
input rw;
input [23:0] ad;
inout tri [7:0] db;
output rdy;
 
reg [7:0] cmd;
reg [7:0] state;
reg [5:0] state_stk [3:0];
//reg [3:0] sp;
reg [1:0] sign;
reg [EMSB:0] acc;
reg [7:0] y;
reg [EMSB+FMSB+1:0] FAC1;
reg [EMSB+FMSB+1:0] FAC2;
reg [FMSB:0] E;
wire [EMSB:0] FAC1_exp = FAC1[EMSB+FMSB+1:FMSB+1];
wire [FMSB:0] FAC1_man = FAC1[FMSB:0];
wire [EMSB:0] FAC2_exp = FAC2[EMSB+FMSB+1:FMSB+1];
wire [FMSB:0] FAC2_man = FAC2[FMSB:0];
 
reg addOrSub;
wire [FMSB+1:0] sum = addOrSub ? FAC2_man - FAC1_man : FAC2_man + FAC1_man;
wire [FMSB+1:0] dif = FAC2_man - E;
wire [FMSB+1:0] neg = {FMSB+1{1'b0}} - FAC1_man;
wire [EMSB+1:0] expdif = FAC2_exp - FAC1_exp;
// Note the carry flag must be extended manually!
reg cf,vf,nf;
wire [EMSB+1:0] exp_sum = acc + FAC1_exp + {15'd0,cf};   // FMUL
wire [EMSB+1:0] exp_dif = acc - FAC1_exp - {15'd0,~cf};  // FDIV
reg [FMSB:0] rem;
reg isRTAR;
reg busy;
reg shiftBy16;
reg isFixedPoint;
reg [7:0] dbo;
 
wire eq = FAC1==FAC2;
wire gt = (FAC1[FMSB]^FAC2[FMSB]) ? FAC2[FMSB] : // If the signs are different, whichever one is positive
                   FAC1_exp==FAC2_exp ? (FAC1_man > FAC2_man) : // if exponents are equal check mantissa
                   FAC1_exp > FAC2_exp; // else compare exponents
wire lt = !(gt|eq);
wire zf = ~|FAC1;
 
wire cs = vda && (ad[23:8]==pIOAddress[23:8]);
reg rdy1,rdy2;
always @(posedge clk)
if (rst) begin
        rdy1 <= 1'b1;
        rdy2 <= 1'b1;
end
else begin
        rdy1 <= cs & ~rdy1;
        rdy2 <= cs & rdy1;
end
assign rdy = cs ? (rw ? rdy2 : 1'b1) : pRdyStyle;
assign db = cs & rw ? dbo : {8{1'bz}};
 
// This is a clock cycle counter used in simulation to determine the number of
// cycles a given operation takes to complete.
reg [11:0] cyccnt;
 
always @(posedge clk)
if (rst) begin
        next_state(RESET);
`ifdef SIMULATION
        FAC1 <= 96'd0;  // for simulation
        FAC2 <= 96'd0;
`endif
end
else begin
`ifdef SIMULATION
        cyccnt <= cyccnt + 1;
`endif
        cmd <= 8'h00;
        if (cs & ~rw)
                case(ad[7:0])
                8'h00:  FAC1[7:0] <= db;
                8'h01:  FAC1[15:8] <= db;
                8'h02:  FAC1[23:16] <= db;
                8'h03:  FAC1[31:24] <= db;
                8'h04:  FAC1[39:32] <= db;
                8'h05:  FAC1[47:40] <= db;
                8'h06:  FAC1[55:48] <= db;
                8'h07:  FAC1[63:56] <= db;
                8'h08:  FAC1[71:64] <= db;
                8'h09:  FAC1[79:72] <= db;
                8'h0A:  FAC1[87:80] <= db;
                8'h0B:  FAC1[95:88] <= db;
                8'h0E:  cmd <= db;
                8'h10:  FAC2[7:0] <= db;
                8'h11:  FAC2[15:8] <= db;
                8'h12:  FAC2[23:16] <= db;
                8'h13:  FAC2[31:24] <= db;
                8'h14:  FAC2[39:32] <= db;
                8'h15:  FAC2[47:40] <= db;
                8'h16:  FAC2[55:48] <= db;
                8'h17:  FAC2[63:56] <= db;
                8'h18:  FAC2[71:64] <= db;
                8'h19:  FAC2[79:72] <= db;
                8'h1A:  FAC2[87:80] <= db;
                8'h1B:  FAC2[95:88] <= db;
                endcase
 
        case(ad[7:0])
        8'h00:  dbo <= FAC1[7:0];
        8'h01:  dbo <= FAC1[15:8];
        8'h02:  dbo <= FAC1[23:16];
        8'h03:  dbo <= FAC1[31:24];
        8'h04:  dbo <= FAC1[39:32];
        8'h05:  dbo <= FAC1[47:40];
        8'h06:  dbo <= FAC1[55:48];
        8'h07:  dbo <= FAC1[63:56];
        8'h08:  dbo <= FAC1[71:64];
        8'h09:  dbo <= FAC1[79:72];
        8'h0A:  dbo <= FAC1[87:80];
        8'h0B:  dbo <= FAC1[95:88];
        8'h0E:  dbo <= {busy,2'b00,lt,eq,gt,zf,vf};
        8'h10:  dbo <= FAC2[7:0];
        8'h11:  dbo <= FAC2[15:8];
        8'h12:  dbo <= FAC2[23:16];
        8'h13:  dbo <= FAC2[31:24];
        8'h14:  dbo <= FAC2[39:32];
        8'h15:  dbo <= FAC2[47:40];
        8'h16:  dbo <= FAC2[55:48];
        8'h17:  dbo <= FAC2[63:56];
        8'h18:  dbo <= FAC2[71:64];
        8'h19:  dbo <= FAC2[79:72];
        8'h1A:  dbo <= FAC2[87:80];
        8'h1B:  dbo <= FAC2[95:88];
        endcase
 
case(state)
RESET:
        begin
//              sp <= 4'h0;
                next_state(IDLE);
        end
 
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
 
IDLE:
        begin
`ifdef SIMULATION
                if (cyccnt > 0)
                        $display("Cycle Count=%d", cyccnt);
                cyccnt <= 12'h0;
`endif
                busy <= 1'b0;
//              sp <= 4'h0;
                isFixedPoint <= FALSE;
                case(cmd)
                FADD:   begin push_state(IDLE); next_state(FADD); busy <= 1'b1; addOrSub <= 1'b0; end
                FSUB:   begin push_state(IDLE); next_state(FSUB); busy <= 1'b1; addOrSub <= 1'b0; end
                FMUL:   begin push_state(IDLE); next_state(FMUL); busy <= 1'b1; addOrSub <= 1'b0; end
                FDIV:   begin push_state(IDLE); next_state(FDIV); busy <= 1'b1; end
                FIX2FLT:        begin push_state(IDLE); next_state(FIX2FLT); busy <= 1'b1; end
                FLT2FIX:        begin push_state(IDLE); next_state(FLT2FIX); busy <= 1'b1; end
                FNEG:           begin push_state(IDLE); next_state(FCOMPL); busy <= 1'b1; end
                FABS:           begin push_state(IDLE); next_state(ABS); busy <= 1'b1; end
                FNABS:          begin push_state(IDLE); next_state(NABS); busy <= 1'b1; end
                SWAP:           begin push_state(IDLE); next_state(SWAP); busy <= 1'b1; end
                // Fixed point operations
                FIXED_ADD:      begin push_state(IDLE); next_state(FADD); busy <= 1'b1; isFixedPoint <= TRUE; addOrSub <= 1'b0; end
                FIXED_SUB:      begin push_state(IDLE); next_state(FSUB); busy <= 1'b1; isFixedPoint <= TRUE; addOrSub <= 1'b0; end
                FIXED_MUL:      begin push_state(IDLE); next_state(FMUL); busy <= 1'b1; isFixedPoint <= TRUE; addOrSub <= 1'b0; end
                FIXED_DIV:      begin push_state(IDLE); next_state(FDIV); busy <= 1'b1; isFixedPoint <= TRUE; end
                FIXED_NEG:      begin push_state(IDLE); next_state(FCOMPL); busy <= 1'b1; isFixedPoint <= TRUE; end
                FIXED_ABS:      begin push_state(IDLE); next_state(ABS); busy <= 1'b1; isFixedPoint <= TRUE; end
                endcase
        end
 
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
 
MD1:
        begin
                $display("MD1");
                sign <= {sign[1:0],1'b0};
                next_state(ABSSWP);
                push_state(ABSSWP);
        end
ABSSWP:
        begin
                if (~FAC1_man[FMSB]) begin
                        next_state(ABSSWP1);
                end
                else begin
                        push_state(ABSSWP1);
                        sign <= sign + 2'd1;
                        next_state(FCOMPL);
                end
        end
ABSSWP1:
        begin
                cf <= 1'b1;
                next_state(SWAP);
        end
 
 
//-----------------------------------------------------------------------------
// Take the absolute value of FAC1
//-----------------------------------------------------------------------------
 
ABS:
        begin
                if (FAC1_man[FMSB])
                        next_state(FCOMPL);
                else
                        pop_state();
        end
 
//-----------------------------------------------------------------------------
// Take the negative absolute value of FAC1
//-----------------------------------------------------------------------------
 
NABS:
        begin
                if (~FAC1_man[FMSB])
                        next_state(FCOMPL);
                else
                        pop_state();
        end
 
//-----------------------------------------------------------------------------
// Normalize
// - Decrement exponent and shift left
// - Normalization is normally the last step of an operation.
// - If possible the FAC is shifted by 16 bits at a time. This helps with
//   the many small constants that are usually present.
//-----------------------------------------------------------------------------
NORM:
        begin
        if (isFixedPoint)       // nothing to do for fixed point
                pop_state();
        else begin
        $display("Normalize FAC1H %h", FAC1[FMSB:FMSB-15]);
        if (FAC1[FMSB]!=FAC1[FMSB-1] || ~|FAC1_exp) begin
                $display("Normal: %h",FAC1);
                pop_state();
        end
        // If the mantissa is zero, set the the exponent to zero. Otherwise 
        // normalization could spin for thousands of clock cycles decrementing
        // the exponent to zero.
        else if (~|FAC1_man) begin
                FAC1[EMSB+FMSB+1:FMSB+1] <= 16'h0;
                pop_state();
        end
        else if (FAC1[FMSB:FMSB-15]=={16{FAC1[FMSB]}}) begin
                $display("shift by 16");
                FAC1[EMSB+FMSB+1:FMSB+1] <= FAC1[EMSB+FMSB+1:FMSB+1] - 16'd16;
                FAC1[FMSB:0] <= {FAC1[FMSB-16:0],16'h0};
        end
        else begin
                FAC1[EMSB+FMSB+1:FMSB+1] <= FAC1[EMSB+FMSB+1:FMSB+1] - 16'd1;
                FAC1[FMSB:0] <= {FAC1[FMSB-1:0],1'b0};
        end
        end
        end
 
//-----------------------------------------------------------------------------
// Add mantissa's and compute carry and overflow.
// This is used by both ADD and MUL.
//-----------------------------------------------------------------------------
 
ADD:
        begin
                FAC1[FMSB:0] <= sum[FMSB:0];
                cf <= sum[FMSB+1];
                vf <= (sum[FMSB] ^ FAC2[FMSB]) & (1'b1 ^ FAC1[FMSB] ^ FAC2[FMSB]);
                pop_state();
        end
 
//-----------------------------------------------------------------------------
// Negate
//-----------------------------------------------------------------------------
 
// Complement FAC1
FCOMPL:
        begin
                $display("FCOMPL");
                FAC1[FMSB:0] <= neg[FMSB:0];
                cf <= ~neg[FMSB+1];
                vf <= neg[FMSB]==FAC1[FMSB];
                if (isFixedPoint)
                        pop_state();
                else
                        next_state(ADDEND);
        end
 
//-----------------------------------------------------------------------------
// Swap FAC1 and FAC2
//-----------------------------------------------------------------------------
 
SWAP:
        begin
                $display("Swapping FAC1 and FAC2");
                FAC1 <= FAC2;
                FAC2 <= FAC1;
                E <= FAC2[FMSB:0];
                acc <= FAC1_exp;
                pop_state();
        end
 
//-----------------------------------------------------------------------------
// Subtract
// - subtract first complements the FAC then performs an ADD operation.
//-----------------------------------------------------------------------------
 
FSUB:
        begin
//              if (isFixedPoint)
//                      push_state(FADD);
//              else
//                      push_state(SWPALG);
                push_state(FADD);
                next_state(FCOMPL);
        end
SWPALG:
        begin
                push_state(FADD);
                next_state(ALGNSW);
        end
 
//-----------------------------------------------------------------------------
// Addition
//-----------------------------------------------------------------------------
 
FADD:
        begin
                cf <= ~expdif[EMSB+1];  // Must set carry flag from compare
                // If the exponents are too different then one of the values will
                // become zero, so the result is just the larger value. This check
                // is to prevent shifting thousands of times.
                if (expdif[15] ? expdif < 16'hFFB0 : expdif[15:0] > 16'h0050) begin
                        FAC1 <= expdif[15] ? FAC2 : FAC1;
                        pop_state();
                end
                else if (|expdif[15:0] & !isFixedPoint)
                        next_state(SWPALG);
                else begin
                        if (!isFixedPoint) push_state(ADDEND);
                        next_state(ADD);
                end
        end
ADDEND:
        begin
                if (!vf)
                        next_state(NORM);
                else begin
                        isRTAR <= FALSE;
                        next_state(RTLOG);
                end
        end
ALGNSW:
        begin
                if (!cf)
                        next_state(SWAP);
                else begin
                        isRTAR <= TRUE;
                        next_state(RTLOG);
                end
        end
 
//-----------------------------------------------------------------------------
// Right shift, logical or arithmetic.
//-----------------------------------------------------------------------------
 
RTLOG:
        begin
                FAC1[EMSB+FMSB+1:FMSB+1] <= FAC1[EMSB+FMSB+1:FMSB+1] + 16'd1;
                if (FAC1[EMSB+FMSB+1:FMSB+1]==16'hFFFF)
                        next_state(OVFL);
                else begin
                        FAC1[FMSB:0] <= {isRTAR ? FAC1_man[FMSB] : cf,FAC1[FMSB:1]};
                        E[FMSB:0] <= {FAC1[0],E[FMSB-1:1]};
                        cf <= E[0];
                        pop_state();
                end
        end
 
//-----------------------------------------------------------------------------
// Mulyiply
//-----------------------------------------------------------------------------
 
FMUL:
        begin
                next_state(MD1);
                push_state(FMUL1);
        end
FMUL1:
        begin
                acc <= exp_sum[EMSB:0];
                cf <= exp_sum[EMSB+1];
                push_state(MUL1);
                next_state(MD2);
        end
MUL1:
        begin
                // inline RTLOG1 code
                FAC1[FMSB:0] <= {1'b0,FAC1[FMSB:1]};
                E[FMSB:0] <= {FAC1[0],E[FMSB-1:1]};
                cf <= E[0];
                next_state(FMUL3);
                //push_state(FMUL3);
                //next_state(RTLOG1);
        end
FMUL3:
        begin
                if (cf) begin
                        FAC1[FMSB:0] <= sum[FMSB:0];
                        cf <= sum[FMSB+1];
                        vf <= (sum[FMSB] ^ FAC2[FMSB]) & (1'b1 ^ FAC1[FMSB] ^ FAC2[FMSB]);
                end
                y <= y - 8'd1;
                if (y==8'd0)
                        next_state(MDEND);
                else
                        next_state(MUL1);
        end
MDEND:
        begin
                sign <= {1'b0,sign[1]};
                if (~sign[0])
                        next_state(NORM);
                else
                        next_state(FCOMPL);
        end
 
//-----------------------------------------------------------------------------
// Divide
//-----------------------------------------------------------------------------
FDIV:
        begin
                push_state(FDIV1);
                next_state(MD1);
        end
FDIV1:
        begin
                acc <= exp_dif[EMSB:0];
                cf <= ~exp_dif[EMSB+1];
                $display("acc=%h %h %h", exp_dif, acc, FAC1_exp);
                push_state(DIV1);
                next_state(MD2);
        end
DIV1:
        begin
                $display("FAC1=%h, FAC2=%h, E=%h", FAC1, FAC2, E);
                y <= y - 8'd1;
                FAC1[FMSB:0] <= {FAC1[FMSB:0],~dif[FMSB+1]};
                if (dif[FMSB+1]) begin
                        FAC2[FMSB:0] <= {FAC2[FMSB-1:0],1'b0};
                        if (FAC2[FMSB]) begin
                                next_state(OVFL);
                        end
                        else if (y!=8'd1)
                                next_state(DIV1);
                        else begin
                                rem <= dif;
                                next_state(MDEND);
                        end
                end
                else begin
                        FAC2[FMSB:0] <= {dif[FMSB-1:0],1'b0};
                        if (dif[FMSB]) begin
                                next_state(OVFL);
                        end
                        else if (y!=8'd1)
                                next_state(DIV1);
                        else begin
                                rem <= dif;
                                next_state(MDEND);
                        end
                end
        end
 
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
MD2:
        begin
                FAC1[FMSB:0] <= 80'h0;
                if (isFixedPoint) begin
                        y <= 8'h4F;
                        pop_state();
                end
                else if (cf)
                        next_state(OVCHK);
                else if (acc[EMSB])
                        next_state(MD3);
                else begin
                        pop_state();
                        next_state(NORM);
                end
        end
MD3:
        begin
                acc[EMSB] <= ~acc[EMSB];
                FAC1[EMSB+FMSB+1:FMSB+1] <= {~acc[EMSB],acc[EMSB-1:0]};
                y <= 8'h4F;
                pop_state();
        end
OVCHK:
        begin
                if (~acc[EMSB])
                        next_state(MD3);
                else
                        next_state(OVFL);
        end
OVFL:
        begin
                vf <= 1'b1;
                next_state(IDLE);
        end
 
//-----------------------------------------------------------------------------
// FIX2FLT
// - convert 64 bit fixed point number to floating point
//-----------------------------------------------------------------------------
 
FIX2FLT:
        begin
                FAC1[EMSB+FMSB+1:FMSB+1] <= 16'h804E;   // exponent = 78
                next_state(NORM);
        end
 
//-----------------------------------------------------------------------------
// FLT2FIX
// - convert floating point number to fixed point.
//-----------------------------------------------------------------------------
 
FLT2FIX:
        begin
                // If the exponent is too small then no amount of shifting will
                // result in a non-zero number. In this case we just set the 
                // FAC to zero. Otherwise FLT2FIX would spin for thousands of cycles
                // until the exponent incremented finally to 803Eh.
                if (FAC1_exp < 16'h7FB0) begin
                        FAC1[79:0] <= 80'd0;
                        FAC1[95:80] <= 16'h804E;
                        pop_state();
                end
                // If the exponent is too large, we can't right shift and the value
                // would overflow a 64-bit integer, so we just set it to the max.
                else if (FAC1_exp > 16'h804E) begin
                        vf <= 1'b1;
                        FAC1[95:80] <= 16'h804E;
                        FAC1[79:0] <= FAC1[79] ? 80'h80000000000000000000 : 80'h7FFFFFFFFFFFFFFFFFFF;
                        pop_state();
                end
                else if (FAC1_exp==16'h804E)
                        pop_state();
                else begin
                        push_state(FLT2FIX);
                        isRTAR <= TRUE;
                        next_state(RTLOG);
                end
        end
endcase
end
 
/*
DIVBY10:
        begin
                FAC2[EMSB+FMSB+1:FMSB+1] <= 16'h8003;
                FAC2[FMSB] <= 1'b0;             // +ve
                FAC2[FMSB-1:75] <= 4'hA;        // 10
                FAC2[74:0] <= 75'd0;
                next_state(FDIV);
        end
*/
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
task push_state;
input [5:0] st;
begin
        state_stk[0] <= st;
        state_stk[1] <= state_stk[0];
        state_stk[2] <= state_stk[1];
        state_stk[3] <= state_stk[2];
//      state_stk[sp-4'd1] <= st;
//      sp <= sp - 4'd1;
end
endtask
 
task pop_state;
begin
        state <= state_stk[0];
        state_stk[0] <= state_stk[1];
        state_stk[1] <= state_stk[2];
        state_stk[2] <= state_stk[3];
        state_stk[3] <= IDLE;
//      next_state(state_stk[sp]);
//      sp <= sp + 4'd1;
end
endtask
 
task next_state;
input [7:0] st;
begin
        state <= st;
end
endtask
 
endmodule

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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [FT816Float.v] - Blame information for rev 70

Line No.	Rev	Author	Line
1	3	robfinch	`timescale 1ns / 1ps
2			`// ============================================================================`
3			`// __`
4			`// \\__/ o\ (C) 2014 Robert Finch, Stratford`
5			`// \ __ / All rights reserved.`
6			`// \/_// robfinch<remove>@finitron.ca`
7			`// \|\|`
8			`//`
9			`// FT816Float.v`
10			`// - Triple precision floating point accelerator`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`// 1600 LUTs 350 FF's`
26			`// 140 MHz`
27			`// ============================================================================`
28			`//`
29			`define SIMULATION 1'b1
30
31			`module FT816Float(rst, clk, vda, rw, ad, db, rdy);`
32			`parameter pIOAddress = 24'hFEA200;`
33			`parameter pRdyStyle = 1'b1;`
34			`parameter EMSB = 15;`
35			`parameter FMSB = 79;`
36			`parameter TRUE = 1'b1;`
37			`parameter FALSE = 1'b0;`
38			`parameter FADD = 8'd1;`
39			`parameter FSUB = 8'd2;`
40			`parameter FMUL = 8'd3;`
41			`parameter FDIV = 8'd4;`
42			`parameter FIX2FLT = 8'd5;`
43			`parameter FLT2FIX = 8'd6;`
44			`parameter FABS = 8'd7;`
45			`parameter ABS = 8'd7;`
46			`parameter NABS = 8'd8;`
47			`parameter FNABS = 8'd8;`
48			`parameter MD1 = 8'd10;`
49			`parameter ABSSWP = 8'd11;`
50			`parameter ABSSWP1 = 8'd12;`
51			`parameter NORM1 = 8'd13;`
52			`parameter NORM = 8'd14;`
53			`parameter ADD = 8'd15;`
54			`parameter FCOMPL = 8'd16;`
55			`parameter FNEG = 8'd16;`
56			`parameter SWAP = 8'd17;`
57			`parameter FIXED_ADD = 8'h81;`
58			`parameter FIXED_SUB = 8'h82;`
59			`parameter FIXED_MUL = 8'h83;`
60			`parameter FIXED_DIV = 8'h84;`
61			`parameter FIXED_ABS = 8'h87;`
62			`parameter FIXED_NEG = 8'h90;`
63			`parameter SWPALG = 8'd18;`
64			`parameter ADDEND = 8'd19;`
65			`parameter ALGNSW = 8'd20;`
66			`parameter RTLOG = 8'd22;`
67			`parameter FMUL1 = 8'd24;`
68			`parameter FMUL2 = 8'd25;`
69			`parameter MUL1 = 8'd26;`
70			`parameter FMUL3 = 8'd27;`
71			`parameter MUL2 = 8'd28;`
72			`parameter MDEND = 8'd29;`
73			`parameter FDIV1 = 8'd30;`
74			`parameter MD2 = 8'd31;`
75			`parameter MD3 = 8'd32;`
76			`parameter OVCHK = 8'd34;`
77			`parameter OVFL = 8'd35;`
78			`parameter DIV1 = 8'd36;`
79			`parameter IDLE = 8'd62;`
80			`parameter RESET = 8'd63;`
81
82			`input rst;`
83			`input clk;`
84			`input vda;`
85			`input rw;`
86			`input [23:0] ad;`
87			`inout tri [7:0] db;`
88			`output rdy;`
89
90			`reg [7:0] cmd;`
91			`reg [7:0] state;`
92			`reg [5:0] state_stk [3:0];`
93			`//reg [3:0] sp;`
94			`reg [1:0] sign;`
95			`reg [EMSB:0] acc;`
96			`reg [7:0] y;`
97			`reg [EMSB+FMSB+1:0] FAC1;`
98			`reg [EMSB+FMSB+1:0] FAC2;`
99			`reg [FMSB:0] E;`
100			`wire [EMSB:0] FAC1_exp = FAC1[EMSB+FMSB+1:FMSB+1];`
101			`wire [FMSB:0] FAC1_man = FAC1[FMSB:0];`
102			`wire [EMSB:0] FAC2_exp = FAC2[EMSB+FMSB+1:FMSB+1];`
103			`wire [FMSB:0] FAC2_man = FAC2[FMSB:0];`
104
105			`reg addOrSub;`
106			`wire [FMSB+1:0] sum = addOrSub ? FAC2_man - FAC1_man : FAC2_man + FAC1_man;`
107			`wire [FMSB+1:0] dif = FAC2_man - E;`
108			`wire [FMSB+1:0] neg = {FMSB+1{1'b0}} - FAC1_man;`
109			`wire [EMSB+1:0] expdif = FAC2_exp - FAC1_exp;`
110			`// Note the carry flag must be extended manually!`
111			`reg cf,vf,nf;`
112			`wire [EMSB+1:0] exp_sum = acc + FAC1_exp + {15'd0,cf}; // FMUL`
113			`wire [EMSB+1:0] exp_dif = acc - FAC1_exp - {15'd0,~cf}; // FDIV`
114			`reg [FMSB:0] rem;`
115			`reg isRTAR;`
116			`reg busy;`
117			`reg shiftBy16;`
118			`reg isFixedPoint;`
119			`reg [7:0] dbo;`
120
121			`wire eq = FAC1==FAC2;`
122			`wire gt = (FAC1[FMSB]^FAC2[FMSB]) ? FAC2[FMSB] : // If the signs are different, whichever one is positive`
123			`FAC1_exp==FAC2_exp ? (FAC1_man > FAC2_man) : // if exponents are equal check mantissa`
124			`FAC1_exp > FAC2_exp; // else compare exponents`
125			`wire lt = !(gt\|eq);`
126			`wire zf = ~\|FAC1;`
127
128			`wire cs = vda && (ad[23:8]==pIOAddress[23:8]);`
129			`reg rdy1,rdy2;`
130			`always @(posedge clk)`
131			`if (rst) begin`
132			`rdy1 <= 1'b1;`
133			`rdy2 <= 1'b1;`
134			`end`
135			`else begin`
136			`rdy1 <= cs & ~rdy1;`
137			`rdy2 <= cs & rdy1;`
138			`end`
139			`assign rdy = cs ? (rw ? rdy2 : 1'b1) : pRdyStyle;`
140			`assign db = cs & rw ? dbo : {8{1'bz}};`
141
142			`// This is a clock cycle counter used in simulation to determine the number of`
143			`// cycles a given operation takes to complete.`
144			`reg [11:0] cyccnt;`
145
146			`always @(posedge clk)`
147			`if (rst) begin`
148			`next_state(RESET);`
149			`ifdef SIMULATION
150			`FAC1 <= 96'd0; // for simulation`
151			`FAC2 <= 96'd0;`
152			`endif
153			`end`
154			`else begin`
155			`ifdef SIMULATION
156			`cyccnt <= cyccnt + 1;`
157			`endif
158			`cmd <= 8'h00;`
159			`if (cs & ~rw)`
160			`case(ad[7:0])`
161			`8'h00: FAC1[7:0] <= db;`
162			`8'h01: FAC1[15:8] <= db;`
163			`8'h02: FAC1[23:16] <= db;`
164			`8'h03: FAC1[31:24] <= db;`
165			`8'h04: FAC1[39:32] <= db;`
166			`8'h05: FAC1[47:40] <= db;`
167			`8'h06: FAC1[55:48] <= db;`
168			`8'h07: FAC1[63:56] <= db;`
169			`8'h08: FAC1[71:64] <= db;`
170			`8'h09: FAC1[79:72] <= db;`
171			`8'h0A: FAC1[87:80] <= db;`
172			`8'h0B: FAC1[95:88] <= db;`
173			`8'h0E: cmd <= db;`
174			`8'h10: FAC2[7:0] <= db;`
175			`8'h11: FAC2[15:8] <= db;`
176			`8'h12: FAC2[23:16] <= db;`
177			`8'h13: FAC2[31:24] <= db;`
178			`8'h14: FAC2[39:32] <= db;`
179			`8'h15: FAC2[47:40] <= db;`
180			`8'h16: FAC2[55:48] <= db;`
181			`8'h17: FAC2[63:56] <= db;`
182			`8'h18: FAC2[71:64] <= db;`
183			`8'h19: FAC2[79:72] <= db;`
184			`8'h1A: FAC2[87:80] <= db;`
185			`8'h1B: FAC2[95:88] <= db;`
186			`endcase`
187
188			`case(ad[7:0])`
189			`8'h00: dbo <= FAC1[7:0];`
190			`8'h01: dbo <= FAC1[15:8];`
191			`8'h02: dbo <= FAC1[23:16];`
192			`8'h03: dbo <= FAC1[31:24];`
193			`8'h04: dbo <= FAC1[39:32];`
194			`8'h05: dbo <= FAC1[47:40];`
195			`8'h06: dbo <= FAC1[55:48];`
196			`8'h07: dbo <= FAC1[63:56];`
197			`8'h08: dbo <= FAC1[71:64];`
198			`8'h09: dbo <= FAC1[79:72];`
199			`8'h0A: dbo <= FAC1[87:80];`
200			`8'h0B: dbo <= FAC1[95:88];`
201			`8'h0E: dbo <= {busy,2'b00,lt,eq,gt,zf,vf};`
202			`8'h10: dbo <= FAC2[7:0];`
203			`8'h11: dbo <= FAC2[15:8];`
204			`8'h12: dbo <= FAC2[23:16];`
205			`8'h13: dbo <= FAC2[31:24];`
206			`8'h14: dbo <= FAC2[39:32];`
207			`8'h15: dbo <= FAC2[47:40];`
208			`8'h16: dbo <= FAC2[55:48];`
209			`8'h17: dbo <= FAC2[63:56];`
210			`8'h18: dbo <= FAC2[71:64];`
211			`8'h19: dbo <= FAC2[79:72];`
212			`8'h1A: dbo <= FAC2[87:80];`
213			`8'h1B: dbo <= FAC2[95:88];`
214			`endcase`
215
216			`case(state)`
217			`RESET:`
218			`begin`
219			`// sp <= 4'h0;`
220			`next_state(IDLE);`
221			`end`
222
223			`//-----------------------------------------------------------------------------`
224			`//-----------------------------------------------------------------------------`
225
226			`IDLE:`
227			`begin`
228			`ifdef SIMULATION
229			`if (cyccnt > 0)`
230			`$display("Cycle Count=%d", cyccnt);`
231			`cyccnt <= 12'h0;`
232			`endif
233			`busy <= 1'b0;`
234			`// sp <= 4'h0;`
235			`isFixedPoint <= FALSE;`
236			`case(cmd)`
237			`FADD: begin push_state(IDLE); next_state(FADD); busy <= 1'b1; addOrSub <= 1'b0; end`
238			`FSUB: begin push_state(IDLE); next_state(FSUB); busy <= 1'b1; addOrSub <= 1'b0; end`
239			`FMUL: begin push_state(IDLE); next_state(FMUL); busy <= 1'b1; addOrSub <= 1'b0; end`
240			`FDIV: begin push_state(IDLE); next_state(FDIV); busy <= 1'b1; end`
241			`FIX2FLT: begin push_state(IDLE); next_state(FIX2FLT); busy <= 1'b1; end`
242			`FLT2FIX: begin push_state(IDLE); next_state(FLT2FIX); busy <= 1'b1; end`
243			`FNEG: begin push_state(IDLE); next_state(FCOMPL); busy <= 1'b1; end`
244			`FABS: begin push_state(IDLE); next_state(ABS); busy <= 1'b1; end`
245			`FNABS: begin push_state(IDLE); next_state(NABS); busy <= 1'b1; end`
246			`SWAP: begin push_state(IDLE); next_state(SWAP); busy <= 1'b1; end`
247			`// Fixed point operations`
248			`FIXED_ADD: begin push_state(IDLE); next_state(FADD); busy <= 1'b1; isFixedPoint <= TRUE; addOrSub <= 1'b0; end`
249			`FIXED_SUB: begin push_state(IDLE); next_state(FSUB); busy <= 1'b1; isFixedPoint <= TRUE; addOrSub <= 1'b0; end`
250			`FIXED_MUL: begin push_state(IDLE); next_state(FMUL); busy <= 1'b1; isFixedPoint <= TRUE; addOrSub <= 1'b0; end`
251			`FIXED_DIV: begin push_state(IDLE); next_state(FDIV); busy <= 1'b1; isFixedPoint <= TRUE; end`
252			`FIXED_NEG: begin push_state(IDLE); next_state(FCOMPL); busy <= 1'b1; isFixedPoint <= TRUE; end`
253			`FIXED_ABS: begin push_state(IDLE); next_state(ABS); busy <= 1'b1; isFixedPoint <= TRUE; end`
254			`endcase`
255			`end`
256
257			`//-----------------------------------------------------------------------------`
258			`//-----------------------------------------------------------------------------`
259
260			`MD1:`
261			`begin`
262			`$display("MD1");`
263			`sign <= {sign[1:0],1'b0};`
264			`next_state(ABSSWP);`
265			`push_state(ABSSWP);`
266			`end`
267			`ABSSWP:`
268			`begin`
269			`if (~FAC1_man[FMSB]) begin`
270			`next_state(ABSSWP1);`
271			`end`
272			`else begin`
273			`push_state(ABSSWP1);`
274			`sign <= sign + 2'd1;`
275			`next_state(FCOMPL);`
276			`end`
277			`end`
278			`ABSSWP1:`
279			`begin`
280			`cf <= 1'b1;`
281			`next_state(SWAP);`
282			`end`
283
284
285			`//-----------------------------------------------------------------------------`
286			`// Take the absolute value of FAC1`
287			`//-----------------------------------------------------------------------------`
288
289			`ABS:`
290			`begin`
291			`if (FAC1_man[FMSB])`
292			`next_state(FCOMPL);`
293			`else`
294			`pop_state();`
295			`end`
296
297			`//-----------------------------------------------------------------------------`
298			`// Take the negative absolute value of FAC1`
299			`//-----------------------------------------------------------------------------`
300
301			`NABS:`
302			`begin`
303			`if (~FAC1_man[FMSB])`
304			`next_state(FCOMPL);`
305			`else`
306			`pop_state();`
307			`end`
308
309			`//-----------------------------------------------------------------------------`
310			`// Normalize`
311			`// - Decrement exponent and shift left`
312			`// - Normalization is normally the last step of an operation.`
313			`// - If possible the FAC is shifted by 16 bits at a time. This helps with`
314			`// the many small constants that are usually present.`
315			`//-----------------------------------------------------------------------------`
316			`NORM:`
317			`begin`
318			`if (isFixedPoint) // nothing to do for fixed point`
319			`pop_state();`
320			`else begin`
321			`$display("Normalize FAC1H %h", FAC1[FMSB:FMSB-15]);`
322			`if (FAC1[FMSB]!=FAC1[FMSB-1] \|\| ~\|FAC1_exp) begin`
323			`$display("Normal: %h",FAC1);`
324			`pop_state();`
325			`end`
326			`// If the mantissa is zero, set the the exponent to zero. Otherwise`
327			`// normalization could spin for thousands of clock cycles decrementing`
328			`// the exponent to zero.`
329			`else if (~\|FAC1_man) begin`
330			`FAC1[EMSB+FMSB+1:FMSB+1] <= 16'h0;`
331			`pop_state();`
332			`end`
333			`else if (FAC1[FMSB:FMSB-15]=={16{FAC1[FMSB]}}) begin`
334			`$display("shift by 16");`
335			`FAC1[EMSB+FMSB+1:FMSB+1] <= FAC1[EMSB+FMSB+1:FMSB+1] - 16'd16;`
336			`FAC1[FMSB:0] <= {FAC1[FMSB-16:0],16'h0};`
337			`end`
338			`else begin`
339			`FAC1[EMSB+FMSB+1:FMSB+1] <= FAC1[EMSB+FMSB+1:FMSB+1] - 16'd1;`
340			`FAC1[FMSB:0] <= {FAC1[FMSB-1:0],1'b0};`
341			`end`
342			`end`
343			`end`
344
345			`//-----------------------------------------------------------------------------`
346			`// Add mantissa's and compute carry and overflow.`
347			`// This is used by both ADD and MUL.`
348			`//-----------------------------------------------------------------------------`
349
350			`ADD:`
351			`begin`
352			`FAC1[FMSB:0] <= sum[FMSB:0];`
353			`cf <= sum[FMSB+1];`
354			`vf <= (sum[FMSB] ^ FAC2[FMSB]) & (1'b1 ^ FAC1[FMSB] ^ FAC2[FMSB]);`
355			`pop_state();`
356			`end`
357
358			`//-----------------------------------------------------------------------------`
359			`// Negate`
360			`//-----------------------------------------------------------------------------`
361
362			`// Complement FAC1`
363			`FCOMPL:`
364			`begin`
365			`$display("FCOMPL");`
366			`FAC1[FMSB:0] <= neg[FMSB:0];`
367			`cf <= ~neg[FMSB+1];`
368			`vf <= neg[FMSB]==FAC1[FMSB];`
369			`if (isFixedPoint)`
370			`pop_state();`
371			`else`
372			`next_state(ADDEND);`
373			`end`
374
375			`//-----------------------------------------------------------------------------`
376			`// Swap FAC1 and FAC2`
377			`//-----------------------------------------------------------------------------`
378
379			`SWAP:`
380			`begin`
381			`$display("Swapping FAC1 and FAC2");`
382			`FAC1 <= FAC2;`
383			`FAC2 <= FAC1;`
384			`E <= FAC2[FMSB:0];`
385			`acc <= FAC1_exp;`
386			`pop_state();`
387			`end`
388
389			`//-----------------------------------------------------------------------------`
390			`// Subtract`
391			`// - subtract first complements the FAC then performs an ADD operation.`
392			`//-----------------------------------------------------------------------------`
393
394			`FSUB:`
395			`begin`
396			`// if (isFixedPoint)`
397			`// push_state(FADD);`
398			`// else`
399			`// push_state(SWPALG);`
400			`push_state(FADD);`
401			`next_state(FCOMPL);`
402			`end`
403			`SWPALG:`
404			`begin`
405			`push_state(FADD);`
406			`next_state(ALGNSW);`
407			`end`
408
409			`//-----------------------------------------------------------------------------`
410			`// Addition`
411			`//-----------------------------------------------------------------------------`
412
413			`FADD:`
414			`begin`
415			`cf <= ~expdif[EMSB+1]; // Must set carry flag from compare`
416			`// If the exponents are too different then one of the values will`
417			`// become zero, so the result is just the larger value. This check`
418			`// is to prevent shifting thousands of times.`
419			`if (expdif[15] ? expdif < 16'hFFB0 : expdif[15:0] > 16'h0050) begin`
420			`FAC1 <= expdif[15] ? FAC2 : FAC1;`
421			`pop_state();`
422			`end`
423			`else if (\|expdif[15:0] & !isFixedPoint)`
424			`next_state(SWPALG);`
425			`else begin`
426			`if (!isFixedPoint) push_state(ADDEND);`
427			`next_state(ADD);`
428			`end`
429			`end`
430			`ADDEND:`
431			`begin`
432			`if (!vf)`
433			`next_state(NORM);`
434			`else begin`
435			`isRTAR <= FALSE;`
436			`next_state(RTLOG);`
437			`end`
438			`end`
439			`ALGNSW:`
440			`begin`
441			`if (!cf)`
442			`next_state(SWAP);`
443			`else begin`
444			`isRTAR <= TRUE;`
445			`next_state(RTLOG);`
446			`end`
447			`end`
448
449			`//-----------------------------------------------------------------------------`
450			`// Right shift, logical or arithmetic.`
451			`//-----------------------------------------------------------------------------`
452
453			`RTLOG:`
454			`begin`
455			`FAC1[EMSB+FMSB+1:FMSB+1] <= FAC1[EMSB+FMSB+1:FMSB+1] + 16'd1;`
456			`if (FAC1[EMSB+FMSB+1:FMSB+1]==16'hFFFF)`
457			`next_state(OVFL);`
458			`else begin`
459			`FAC1[FMSB:0] <= {isRTAR ? FAC1_man[FMSB] : cf,FAC1[FMSB:1]};`
460			`E[FMSB:0] <= {FAC1[0],E[FMSB-1:1]};`
461			`cf <= E[0];`
462			`pop_state();`
463			`end`
464			`end`
465
466			`//-----------------------------------------------------------------------------`
467			`// Mulyiply`
468			`//-----------------------------------------------------------------------------`
469
470			`FMUL:`
471			`begin`
472			`next_state(MD1);`
473			`push_state(FMUL1);`
474			`end`
475			`FMUL1:`
476			`begin`
477			`acc <= exp_sum[EMSB:0];`
478			`cf <= exp_sum[EMSB+1];`
479			`push_state(MUL1);`
480			`next_state(MD2);`
481			`end`
482			`MUL1:`
483			`begin`
484			`// inline RTLOG1 code`
485			`FAC1[FMSB:0] <= {1'b0,FAC1[FMSB:1]};`
486			`E[FMSB:0] <= {FAC1[0],E[FMSB-1:1]};`
487			`cf <= E[0];`
488			`next_state(FMUL3);`
489			`//push_state(FMUL3);`
490			`//next_state(RTLOG1);`
491			`end`
492			`FMUL3:`
493			`begin`
494			`if (cf) begin`
495			`FAC1[FMSB:0] <= sum[FMSB:0];`
496			`cf <= sum[FMSB+1];`
497			`vf <= (sum[FMSB] ^ FAC2[FMSB]) & (1'b1 ^ FAC1[FMSB] ^ FAC2[FMSB]);`
498			`end`
499			`y <= y - 8'd1;`
500			`if (y==8'd0)`
501			`next_state(MDEND);`
502			`else`
503			`next_state(MUL1);`
504			`end`
505			`MDEND:`
506			`begin`
507			`sign <= {1'b0,sign[1]};`
508			`if (~sign[0])`
509			`next_state(NORM);`
510			`else`
511			`next_state(FCOMPL);`
512			`end`
513
514			`//-----------------------------------------------------------------------------`
515			`// Divide`
516			`//-----------------------------------------------------------------------------`
517			`FDIV:`
518			`begin`
519			`push_state(FDIV1);`
520			`next_state(MD1);`
521			`end`
522			`FDIV1:`
523			`begin`
524			`acc <= exp_dif[EMSB:0];`
525			`cf <= ~exp_dif[EMSB+1];`
526			`$display("acc=%h %h %h", exp_dif, acc, FAC1_exp);`
527			`push_state(DIV1);`
528			`next_state(MD2);`
529			`end`
530			`DIV1:`
531			`begin`
532			`$display("FAC1=%h, FAC2=%h, E=%h", FAC1, FAC2, E);`
533			`y <= y - 8'd1;`
534			`FAC1[FMSB:0] <= {FAC1[FMSB:0],~dif[FMSB+1]};`
535			`if (dif[FMSB+1]) begin`
536			`FAC2[FMSB:0] <= {FAC2[FMSB-1:0],1'b0};`
537			`if (FAC2[FMSB]) begin`
538			`next_state(OVFL);`
539			`end`
540			`else if (y!=8'd1)`
541			`next_state(DIV1);`
542			`else begin`
543			`rem <= dif;`
544			`next_state(MDEND);`
545			`end`
546			`end`
547			`else begin`
548			`FAC2[FMSB:0] <= {dif[FMSB-1:0],1'b0};`
549			`if (dif[FMSB]) begin`
550			`next_state(OVFL);`
551			`end`
552			`else if (y!=8'd1)`
553			`next_state(DIV1);`
554			`else begin`
555			`rem <= dif;`
556			`next_state(MDEND);`
557			`end`
558			`end`
559			`end`
560
561			`//-----------------------------------------------------------------------------`
562			`//-----------------------------------------------------------------------------`
563			`MD2:`
564			`begin`
565			`FAC1[FMSB:0] <= 80'h0;`
566			`if (isFixedPoint) begin`
567			`y <= 8'h4F;`
568			`pop_state();`
569			`end`
570			`else if (cf)`
571			`next_state(OVCHK);`
572			`else if (acc[EMSB])`
573			`next_state(MD3);`
574			`else begin`
575			`pop_state();`
576			`next_state(NORM);`
577			`end`
578			`end`
579			`MD3:`
580			`begin`
581			`acc[EMSB] <= ~acc[EMSB];`
582			`FAC1[EMSB+FMSB+1:FMSB+1] <= {~acc[EMSB],acc[EMSB-1:0]};`
583			`y <= 8'h4F;`
584			`pop_state();`
585			`end`
586			`OVCHK:`
587			`begin`
588			`if (~acc[EMSB])`
589			`next_state(MD3);`
590			`else`
591			`next_state(OVFL);`
592			`end`
593			`OVFL:`
594			`begin`
595			`vf <= 1'b1;`
596			`next_state(IDLE);`
597			`end`
598
599			`//-----------------------------------------------------------------------------`
600			`// FIX2FLT`
601			`// - convert 64 bit fixed point number to floating point`
602			`//-----------------------------------------------------------------------------`
603
604			`FIX2FLT:`
605			`begin`
606			`FAC1[EMSB+FMSB+1:FMSB+1] <= 16'h804E; // exponent = 78`
607			`next_state(NORM);`
608			`end`
609
610			`//-----------------------------------------------------------------------------`
611			`// FLT2FIX`
612			`// - convert floating point number to fixed point.`
613			`//-----------------------------------------------------------------------------`
614
615			`FLT2FIX:`
616			`begin`
617			`// If the exponent is too small then no amount of shifting will`
618			`// result in a non-zero number. In this case we just set the`
619			`// FAC to zero. Otherwise FLT2FIX would spin for thousands of cycles`
620			`// until the exponent incremented finally to 803Eh.`
621			`if (FAC1_exp < 16'h7FB0) begin`
622			`FAC1[79:0] <= 80'd0;`
623			`FAC1[95:80] <= 16'h804E;`
624			`pop_state();`
625			`end`
626			`// If the exponent is too large, we can't right shift and the value`
627			`// would overflow a 64-bit integer, so we just set it to the max.`
628			`else if (FAC1_exp > 16'h804E) begin`
629			`vf <= 1'b1;`
630			`FAC1[95:80] <= 16'h804E;`
631			`FAC1[79:0] <= FAC1[79] ? 80'h80000000000000000000 : 80'h7FFFFFFFFFFFFFFFFFFF;`
632			`pop_state();`
633			`end`
634			`else if (FAC1_exp==16'h804E)`
635			`pop_state();`
636			`else begin`
637			`push_state(FLT2FIX);`
638			`isRTAR <= TRUE;`
639			`next_state(RTLOG);`
640			`end`
641			`end`
642			`endcase`
643			`end`
644
645			`/*`
646			`DIVBY10:`
647			`begin`
648			`FAC2[EMSB+FMSB+1:FMSB+1] <= 16'h8003;`
649			`FAC2[FMSB] <= 1'b0; // +ve`
650			`FAC2[FMSB-1:75] <= 4'hA; // 10`
651			`FAC2[74:0] <= 75'd0;`
652			`next_state(FDIV);`
653			`end`
654			`*/`
655			`//-----------------------------------------------------------------------------`
656			`//-----------------------------------------------------------------------------`
657			`task push_state;`
658			`input [5:0] st;`
659			`begin`
660			`state_stk[0] <= st;`
661			`state_stk[1] <= state_stk[0];`
662			`state_stk[2] <= state_stk[1];`
663			`state_stk[3] <= state_stk[2];`
664			`// state_stk[sp-4'd1] <= st;`
665			`// sp <= sp - 4'd1;`
666			`end`
667			`endtask`
668
669			`task pop_state;`
670			`begin`
671			`state <= state_stk[0];`
672			`state_stk[0] <= state_stk[1];`
673			`state_stk[1] <= state_stk[2];`
674			`state_stk[2] <= state_stk[3];`
675			`state_stk[3] <= IDLE;`
676			`// next_state(state_stk[sp]);`
677			`// sp <= sp + 4'd1;`
678			`end`
679			`endtask`
680
681			`task next_state;`
682			`input [7:0] st;`
683			`begin`
684			`state <= st;`
685			`end`
686			`endtask`
687
688			`endmodule`