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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [FloatToInt.v] - Blame information for rev 84

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1 5 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2016  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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// FloatToInt
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// - convert floating point to integer
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// - Can convert a number on every clock cycle, with a latency of one cycle.
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// - parameterized width
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// - IEEE 754 representation
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//
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// The WID parameter should be either 32 or 64
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// ============================================================================
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//
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module FloatToInt(clk, ce, i, o, overflow);
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parameter WID = 32;
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input clk;
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input ce;
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input [WID-1:0] i;
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output [WID-1:0] o;
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output overflow;
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localparam MSB = WID-1;
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localparam EMSB =
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          WID==80 ? 14 :
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          WID==64 ? 10 :
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                                  WID==52 ? 10 :
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                                  WID==48 ? 10 :
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                                  WID==44 ? 10 :
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                                  WID==42 ? 10 :
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                                  WID==40 ?  9 :
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                                  WID==32 ?  7 :
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                                  WID==24 ?  6 : 4;
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localparam FMSB =
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          WID==80 ? 63 :
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          WID==64 ? 51 :
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                                  WID==52 ? 39 :
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                                  WID==48 ? 35 :
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                                  WID==44 ? 31 :
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                                  WID==42 ? 29 :
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                                  WID==40 ? 28 :
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                                  WID==32 ? 22 :
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                                  WID==24 ? 15 : 9;
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wire [MSB:0] maxInt  = {MSB{1'b1}};              // maximum unsigned integer value
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wire [EMSB:0] zeroXp = {EMSB{1'b1}};     // simple constant - value of exp for zero
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// Decompose fp value
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reg sgn;                                                                        // sign
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always @(posedge clk)
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        if (ce) sgn = i[MSB];
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wire [EMSB:0] exp = i[MSB-1:FMSB+1];             // exponent
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wire [FMSB+1:0] man = {exp!=0,i[FMSB:0]};  // mantissa including recreate hidden bit
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wire iz = i[MSB-1:0]==0;                                  // zero value (special)
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assign overflow  = exp - zeroXp > MSB;          // lots of numbers are too big - don't forget one less bit is available due to signed values
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wire underflow = exp < zeroXp - 1;                      // value less than 1/2
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wire [6:0] shamt = MSB - (exp - zeroXp); // exp - zeroXp will be <= MSB
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wire [MSB+1:0] o1 = {man,{EMSB+1{1'b0}},1'b0} >> shamt;  // keep an extra bit for rounding
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wire [MSB:0] o2 = o1[MSB+1:1] + o1[0];            // round up
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reg [MSB:0] o3;
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always @(posedge clk)
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        if (ce) begin
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                if (underflow|iz)
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                        o3 <= 0;
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                else if (overflow)
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                        o3 <= maxInt;
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                // value between 1/2 and 1 - round up
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                else if (exp==zeroXp-1)
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                        o3 <= 1;
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                // value > 1
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                else
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                        o3 <= o2;
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        end
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assign o = sgn ? -o3 : o3;                                      // adjust output for correct signed value
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endmodule
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module FloatToInt_tb();
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wire ov1,ov2,ov3,ov4,ov5,ov6;
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wire [31:0] io1,io2,io3,io4,io5,io6;
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reg clk;
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initial begin
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        clk = 0;
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end
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always #10 clk = ~clk;
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FloatToInt #(32) u1 (.clk(clk), .ce(1'b1), .i(32'h3F800000), .o(io1), .overflow(ov1) ); // 1
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FloatToInt #(32) u2 (.clk(clk), .ce(1'b1), .i(32'h00000000), .o(io2), .overflow(ov2) ); // zero should result in zero
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FloatToInt #(32) u3 (.clk(clk), .ce(1'b1), .i(32'h4b3c614e), .o(io3), .overflow(ov3) ); // 12345678
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endmodule

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