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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpAddsub_tb.v] - Blame information for rev 29

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1 10 robfinch
module fpAddsub_tb();
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reg rst;
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reg clk;
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reg [12:0] adr;
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reg [95:0] mem [0:8191];
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reg [95:0] memo [0:9000];
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reg [31:0] a,b,a6,b6;
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wire [31:0] a5,b5;
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wire [31:0] o;
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initial begin
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        rst = 1'b0;
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        clk = 1'b0;
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        adr = 0;
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        $readmemh("c:/cores5/ft64/trunk/rtl/fpUnit/fpAddsub_tv.txt", mem);
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        #20 rst = 1;
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        #50 rst = 0;
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end
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always #5
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        clk = ~clk;
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delay4 #(32) u2 (clk, 1'b1, a, a5);
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delay4 #(32) u3 (clk, 1'b1, b, b5);
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always @(posedge clk)
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if (rst)
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        adr = 0;
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else
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begin
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        adr <= adr + 1;
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        a <= mem[adr][31: 0];
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        b <= mem[adr][63:32];
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        a6 <= a5;
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        b6 <= b5;
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        if (adr > 5)
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                memo[adr-6] <= {o,b5,a5};
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        if (adr==8191) begin
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                $writememh("c:/cores5/ft64/trunk/rtl/fpUnit/fpAddsub_tvo.txt", memo);
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                $finish;
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        end
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end
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fpAddsubnr #(32) u1 (clk, 1'b1, 3'b000, 1'b0, a, b, o);
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endmodule

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