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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpDecompReg.v] - Blame information for rev 77

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`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      fpDecompReg.v
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//    - decompose floating point value with registered outputs
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//    - parameterized width
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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module fpDecomp(i, sgn, exp, man, fract, xz, mz, vz, inf, xinf, qnan, snan, nan);
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parameter WID=32;
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`include "fpSize.sv"
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input [MSB:0] i;
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output sgn;
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output [EMSB:0] exp;
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output [FMSB:0] man;
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output [FMSB+1:0] fract; // mantissa with hidden bit recovered
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output xz;              // denormalized - exponent is zero
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output mz;              // mantissa is zero
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output vz;              // value is zero (both exponent and mantissa are zero)
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output inf;             // all ones exponent, zero mantissa
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output xinf;    // all ones exponent
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output qnan;    // nan
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output snan;    // signalling nan
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output nan;
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// Decompose input
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assign sgn = i[MSB];
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assign exp = i[MSB-1:FMSB+1];
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assign man = i[FMSB:0];
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assign xz = !(|exp);    // denormalized - exponent is zero
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assign mz = !(|man);    // mantissa is zero
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assign vz = xz & mz;    // value is zero (both exponent and mantissa are zero)
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assign inf = &exp & mz; // all ones exponent, zero mantissa
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assign xinf = &exp;
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assign qnan = &exp &  man[FMSB];
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assign snan = &exp & !man[FMSB] & !mz;
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assign nan = &exp & !mz;
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assign fract = {!xz,i[FMSB:0]};
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endmodule
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module fpDecompReg(clk, ce, i, o, sgn, exp, man, fract, xz, mz, vz, inf, xinf, qnan, snan, nan);
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parameter WID=32;
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`include "fpSize.sv"
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input clk;
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input ce;
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input [MSB:0] i;
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output reg [MSB:0] o;
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output reg sgn;
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output reg [EMSB:0] exp;
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output reg [FMSB:0] man;
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output reg [FMSB+1:0] fract;     // mantissa with hidden bit recovered
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output reg xz;          // denormalized - exponent is zero
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output reg mz;          // mantissa is zero
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output reg vz;          // value is zero (both exponent and mantissa are zero)
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output reg inf;         // all ones exponent, zero mantissa
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output reg xinf;        // all ones exponent
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output reg qnan;        // nan
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output reg snan;        // signalling nan
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output reg nan;
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// Decompose input
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always @(posedge clk)
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        if (ce) begin
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                o <= i;
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                sgn = i[MSB];
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                exp = i[MSB-1:FMSB+1];
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                man = i[FMSB:0];
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                xz = !(|exp);   // denormalized - exponent is zero
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                mz = !(|man);   // mantissa is zero
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                vz = xz & mz;   // value is zero (both exponent and mantissa are zero)
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                inf = &exp & mz;        // all ones exponent, zero mantissa
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                xinf = &exp;
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                qnan = &exp &  man[FMSB];
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                snan = &exp & !man[FMSB] & !mz;
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                nan = &exp & !mz;
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                fract = {|exp,i[FMSB:0]};
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        end
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endmodule

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