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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpDecompose.v] - Blame information for rev 85

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1 6 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2016  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//      fpDecompose.v
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//  - decompose floating point value
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//  - parameterized width
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//  - IEEE 754 representation
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//
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// ============================================================================
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//
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module fpDecompose(i, sgn, exp, man, fract, xz, mz, vz, inf, xinf, qnan, snan, nan);
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parameter WID=32;
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localparam MSB  = WID-1;
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localparam EMSB = WID==80 ? 14 :
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                  WID==64 ? 10 :
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                                  WID==52 ? 10 :
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                                  WID==48 ? 10 :
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                                  WID==44 ? 10 :
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                                  WID==42 ? 10 :
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                                  WID==40 ?  9 :
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                                  WID==32 ?  7 :
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                                  WID==24 ?  6 : 4;
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localparam FMSB = WID==80 ? 63 :
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                  WID==64 ? 51 :
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                                  WID==52 ? 39 :
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                                  WID==48 ? 35 :
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                                  WID==44 ? 31 :
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                                  WID==42 ? 29 :
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                                  WID==40 ? 28 :
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                                  WID==32 ? 22 :
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                                  WID==24 ? 15 : 9;
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input [MSB:0] i;
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output sgn;
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output [EMSB:0] exp;
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output [FMSB:0] man;
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output [FMSB+1:0] fract; // mantissa with hidden bit recovered
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output xz;              // denormalized - exponent is zero
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output mz;              // mantissa is zero
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output vz;              // value is zero (both exponent and mantissa are zero)
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output inf;             // all ones exponent, zero mantissa
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output xinf;    // all ones exponent
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output qnan;    // nan
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output snan;    // signalling nan
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output nan;
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// Decompose input
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assign sgn = i[MSB];
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assign exp = i[MSB-1:FMSB+1];
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assign man = i[FMSB:0];
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assign xz = !(|exp);    // denormalized - exponent is zero
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assign mz = !(|man);    // mantissa is zero
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assign vz = xz & mz;    // value is zero (both exponent and mantissa are zero)
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assign inf = &exp & mz; // all ones exponent, zero mantissa
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assign xinf = &exp;
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assign qnan = &exp &  man[FMSB];
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assign snan = &exp & !man[FMSB] & !mz;
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assign nan = &exp & !mz;
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assign fract = {!xz,i[FMSB:0]};
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endmodule
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