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`timescale 1ns / 1ps

// ============================================================================

//        __

//   \\__/ o\    (C) 2006-2018  Robert Finch, Waterloo

//    \  __ /    All rights reserved.

//     \/_//     robfinch<remove>@finitron.ca

//       ||

//

//      fpDiv.v

//    - floating point divider

//    - parameterized width

//    - IEEE 754 representation

//

//

// This source file is free software: you can redistribute it and/or modify 

// it under the terms of the GNU Lesser General Public License as published 

// by the Free Software Foundation, either version 3 of the License, or     

// (at your option) any later version.                                      

//                                                                          

// This source file is distributed in the hope that it will be useful,      

// but WITHOUT ANY WARRANTY; without even the implied warranty of           

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            

// GNU General Public License for more details.                             

//                                                                          

// You should have received a copy of the GNU General Public License        

// along with this program.  If not, see <http://www.gnu.org/licenses/>.    

//                                                                          

//      Floating Point Multiplier / Divider

//

//Properties:

//+-inf * +-inf = -+inf    (this is handled by exOver)

//+-inf * 0     = QNaN

//+-0 / +-0      = QNaN

// ============================================================================

module fpDiv(clk, ce, ld, a, b, o, done, sign_exe, overflow, underflow);

parameter WID = 128;

localparam MSB = WID-1;

localparam EMSB = WID==128 ? 14 :

                  WID==96 ? 14 :

                  WID==80 ? 14 :

                  WID==64 ? 10 :

                                  WID==52 ? 10 :

                                  WID==48 ? 11 :

                                  WID==44 ? 10 :

                                  WID==42 ? 10 :

                                  WID==40 ?  9 :

                                  WID==32 ?  7 :

                                  WID==24 ?  6 : 4;

localparam FMSB = WID==128 ? 111 :

                  WID==96 ? 79 :

                  WID==80 ? 63 :

                  WID==64 ? 51 :

                                  WID==52 ? 39 :

                                  WID==48 ? 34 :

                                  WID==44 ? 31 :

                                  WID==42 ? 29 :

                                  WID==40 ? 28 :

                                  WID==32 ? 22 :

                                  WID==24 ? 15 : 9;

localparam FX = (FMSB+2)*2-1;   // the MSB of the expanded fraction

localparam EX = FX + 1 + EMSB + 1 + 1 - 1;

input clk;

input ce;

input ld;

input [MSB:0] a, b;

output [EX:0] o;

output done;

output sign_exe;

output overflow;

output underflow;

// registered outputs

reg sign_exe;

reg inf;

reg     overflow;

reg     underflow;

reg so;

reg [EMSB:0] xo;

reg [FX:0] mo;

assign o = {so,xo,mo};

// constants

wire [EMSB:0] infXp = {EMSB+1{1'b1}};    // infinite / NaN - all ones

// The following is the value for an exponent of zero, with the offset

// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.

wire [EMSB:0] bias = {1'b0,{EMSB{1'b1}}};        //2^0 exponent

// The following is a template for a quiet nan. (MSB=1)

wire [FMSB:0] qNaN  = {1'b1,{FMSB{1'b0}}};

// variables

wire [EMSB+2:0] ex1;     // sum of exponents

wire [(FMSB+9)*2-1:0] divo;

// Operands

wire sa, sb;                    // sign bit

wire [EMSB:0] xa, xb;    // exponent bits

wire [FMSB+1:0] fracta, fractb;

wire a_dn, b_dn;                        // a/b is denormalized

wire az, bz;

wire aInf, bInf;

wire aNan,bNan;

wire done1;

wire [7:0] lzcnt;

// -----------------------------------------------------------

// - decode the input operands

// - derive basic information

// - calculate exponent

// - calculate fraction

// -----------------------------------------------------------

fpDecomp #(WID) u1a (.i(a), .sgn(sa), .exp(xa), .fract(fracta), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );

fpDecomp #(WID) u1b (.i(b), .sgn(sb), .exp(xb), .fract(fractb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );

// Compute the exponent.

// - correct the exponent for denormalized operands

// - adjust the difference by the bias (add 127)

// - also factor in the different decimal position for division

assign ex1 = (xa|a_dn) - (xb|b_dn) + bias + FMSB + 9 - lzcnt;

// check for exponent underflow/overflow

wire under = ex1[EMSB+2];       // MSB set = negative exponent

wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];

// Perform divide

// could take either 1 or 16 clock cycles

fpdivr8 #(FMSB+9,2) u2 (.clk(clk), .ld(ld), .a({fracta,7'b0}), .b({fractb,7'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));

delay1 #(1) u3 (.clk(clk), .ce(ce), .i(done1), .o(done));

// determine when a NaN is output

wire qNaNOut = (az&bz)|(aInf&bInf);

wire [(FMSB+9)*2-1:0] divo1 = divo[(FMSB+9)*2-1:0] << (lzcnt-2);

always @(posedge clk)

        if (ce) begin

                if (done1) begin

                        casez({qNaNOut|aNan|bNan,bInf,bz,over,under})

                        5'b1????:               xo = infXp;     // NaN exponent value

                        5'b01???:               xo = 0;          // divide by inf

                        5'b001??:               xo = infXp;     // divide by zero

                        5'b0001?:               xo = infXp;     // overflow

                        5'b00001:               xo = 0;          // underflow

                        default:                xo = ex1;       // normal or underflow: passthru neg. exp. for normalization

                        endcase

                        casez({aNan,bNan,qNaNOut,bInf,bz,over})

                        6'b1?????:      mo = {1'b1,a[FMSB:0],{FMSB+1{1'b0}}};

                        6'b01????:      mo = {1'b1,b[FMSB:0],{FMSB+1{1'b0}}};

                        6'b001???:              mo = {1'b1,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};

                        6'b0001??:              mo = 0;  // div by inf

                        6'b00001?:              mo = 0;  // div by zero

                        6'b000001:              mo = 0;  // Inf exponent

                        default:                mo = divo1[(FMSB+9)*2-1:14];    // plain div

                        endcase

                        so              = sa ^ sb;

                        sign_exe        = sa & sb;

                        overflow        = over;

                        underflow       = under;

                end

        end

endmodule

module fpDivnr(clk, ce, ld, a, b, o, rm, done, sign_exe, inf, overflow, underflow);

parameter WID=32;

localparam MSB = WID-1;

localparam EMSB = WID==128 ? 14 :

                  WID==96 ? 14 :

                  WID==80 ? 14 :

                  WID==64 ? 10 :

                                  WID==52 ? 10 :

                                  WID==48 ? 11 :

                                  WID==44 ? 10 :

                                  WID==42 ? 10 :

                                  WID==40 ?  9 :

                                  WID==32 ?  7 :

                                  WID==24 ?  6 : 4;

localparam FMSB = WID==128 ? 111 :

                  WID==96 ? 79 :

                  WID==80 ? 63 :

                  WID==64 ? 51 :

                                  WID==52 ? 39 :

                                  WID==48 ? 34 :

                                  WID==44 ? 31 :

                                  WID==42 ? 29 :

                                  WID==40 ? 28 :

                                  WID==32 ? 22 :

                                  WID==24 ? 15 : 9;

localparam FX = (FMSB+2)*2-1;   // the MSB of the expanded fraction

localparam EX = FX + 1 + EMSB + 1 + 1 - 1;

input clk;

input ce;

input ld;

input  [MSB:0] a, b;

output [MSB:0] o;

input [2:0] rm;

output sign_exe;

output done;

output inf;

output overflow;

output underflow;

wire [EX:0] o1;

wire sign_exe1, inf1, overflow1, underflow1;

wire [MSB+3:0] fpn0;

wire done1;

fpDiv       #(WID) u1 (clk, ce, ld, a, b, o1, done1, sign_exe1, overflow1, underflow1);

fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(underflow1), .i(o1), .o(fpn0) );

fpRoundReg  #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );

delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));

delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));

delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));

delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));

delay2          #(1)   u8(.clk(clk), .ce(ce), .i(done1), .o(done));

endmodule