OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpDiv.v] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2006-2016  Robert Finch, Stratford
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch<remove>@finitron.ca
6
//       ||
7
//
8
// This source file is free software: you can redistribute it and/or modify 
9
// it under the terms of the GNU Lesser General Public License as published 
10
// by the Free Software Foundation, either version 3 of the License, or     
11
// (at your option) any later version.                                      
12
//                                                                          
13
// This source file is distributed in the hope that it will be useful,      
14
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
15
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
16
// GNU General Public License for more details.                             
17
//                                                                          
18
// You should have received a copy of the GNU General Public License        
19
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
20
//
21
//      fpDiv.v
22
//  - floating point divider
23
//  - parameterized width
24
//  - IEEE 754 representation
25
//
26
//      Floating Point Divider
27
//
28
// Properties:
29
// +-0 / +-0    = QNaN
30
//      
31
// ============================================================================
32
//
33
module fpDiv(clk, ce, ld, a, b, o, done, sign_exe, overflow, underflow);
34
 
35
parameter WID = 32;
36
localparam MSB = WID-1;
37
localparam EMSB = WID==80 ? 14 :
38
                  WID==64 ? 10 :
39
                                  WID==52 ? 10 :
40
                                  WID==48 ? 10 :
41
                                  WID==44 ? 10 :
42
                                  WID==42 ? 10 :
43
                                  WID==40 ?  9 :
44
                                  WID==32 ?  7 :
45
                                  WID==24 ?  6 : 4;
46
localparam FMSB = WID==80 ? 63 :
47
                  WID==64 ? 51 :
48
                                  WID==52 ? 39 :
49
                                  WID==48 ? 35 :
50
                                  WID==44 ? 31 :
51
                                  WID==42 ? 29 :
52
                                  WID==40 ? 28 :
53
                                  WID==32 ? 22 :
54
                                  WID==24 ? 15 : 9;
55
 
56
localparam WX = 3;
57
localparam FX = (FMSB+1)*2-1;   // the MSB of the expanded fraction
58
localparam EX = FX + WX + EMSB + 1;
59
 
60
input clk;
61
input ce;
62
input ld;
63
input [MSB:0] a, b;
64
output [EX+1:0] o;
65
output done;
66
output sign_exe;
67
output overflow;
68
output underflow;
69
 
70
// registered outputs
71
reg sign_exe;
72
reg inf;
73
reg     overflow;
74
reg     underflow;
75
 
76
reg so;
77
reg [EMSB:0] xo;
78
reg [FX+WX:0] mo;
79
assign o = {so,xo,mo};
80
 
81
// constants
82
wire [EMSB:0] infXp = {EMSB+1{1'b1}};    // infinite / NaN - all ones
83
// The following is the value for an exponent of zero, with the offset
84
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
85
wire [EMSB:0] bias = {1'b0,{EMSB{1'b1}}};        //2^0 exponent
86
// The following is a template for a quiet nan. (MSB=1)
87
wire [FMSB:0] qNaN  = {1'b1,{FMSB{1'b0}}};
88
 
89
// variables
90
wire [EMSB+2:0] ex1;     // sum of exponents
91
wire [FX+WX:0] divo;
92
 
93
// Operands
94
wire sa, sb;                    // sign bit
95
wire [EMSB:0] xa, xb;    // exponent bits
96
wire [FMSB+1:0] fracta, fractb;
97
wire a_dn, b_dn;                        // a/b is denormalized
98
wire az, bz;
99
wire aInf, bInf;
100
 
101
 
102
// -----------------------------------------------------------
103
// - decode the input operands
104
// - derive basic information
105
// - calculate exponent
106
// - calculate fraction
107
// -----------------------------------------------------------
108
 
109
fpDecompose #(WID) u1a (.i(a), .sgn(sa), .exp(xa), .fract(fracta), .xz(a_dn), .vz(az), .inf(aInf) );
110
fpDecompose #(WID) u1b (.i(b), .sgn(sb), .exp(xb), .fract(fractb), .xz(b_dn), .vz(bz), .inf(bInf) );
111
 
112
// Compute the exponent.
113
// - correct the exponent for denormalized operands
114
// - adjust the difference by the bias (add 127)
115
// - also factor in the different decimal position for division
116
assign ex1 = (xa|a_dn) - (xb|b_dn) + bias + FMSB + 1;
117
 
118
// check for exponent underflow/overflow
119
wire under = ex1[EMSB+2];       // MSB set = negative exponent
120
wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
121
 
122
// Perform divide
123
// could take either 1 or 16 clock cycles
124
fpdivr2 #(FMSB+2) u2 (.clk(clk), .ld(ld), .a(fracta), .b(fractb), .q(divo[(FMSB+1)*2-1:0]), .r(), .done(done));
125
assign divo[FX+WX:(FMSB+1)*2] = 0;
126
 
127
// determine when a NaN is output
128
wire qNaNOut = (az&bz)|(aInf&bInf);
129
 
130
always @(posedge clk)
131
        if (ce) begin
132
                if (done) begin
133
                        casex({qNaNOut,bInf,bz})
134
                        3'b1xx:         xo = infXp;     // NaN exponent value
135
                        3'bx1x:         xo = 0;          // divide by inf
136
                        3'bxx1:         xo = infXp;     // divide by zero
137
                        default:        xo = ex1;               // normal or underflow: passthru neg. exp. for normalization
138
                        endcase
139
 
140
                        casex({qNaNOut,bInf,bz})
141
                        3'b1xx:         mo = {1'b0,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};
142
                        3'bx1x:         mo = 0;  // div by inf
143
                        3'bxx1:         mo = 0;  // div by zero
144
                        default:        mo = divo;              // plain div
145
                        endcase
146
 
147
                        so              = sa ^ sb;
148
                        sign_exe        = sa & sb;
149
                        overflow        = over;
150
                        underflow       = under;
151
                end
152
        end
153
 
154
endmodule
155
 
156
module fpDiv_tb();
157
reg clk;
158
reg ld;
159
wire ce = 1'b1;
160
wire sgnx1,sgnx2,sgnx3,sgnx4,sgnx5,sgnx6;
161
wire inf1,inf2,inf3,inf4,inf5,inf6;
162
wire of1,of2,of3,of4,of5,of6;
163
wire uf1,uf2,uf3,uf4,uf5,uf6;
164
wire [57:0] o1,o2,o3,o4,o5,o6;
165
wire [35:0] o11,o12,o13;
166
wire [31:0] o21,o22,o23;
167
wire done0,done1,done2,done3,done4,done5,done6;
168
 
169
initial begin
170
        clk = 0;
171
        ld = 0;
172
        #20 ld = 1;
173
        #40 ld = 0;
174
end
175
always #10 clk <= ~clk;
176
 
177
fpDiv u1 (.clk(clk), .ce(1'b1), .ld(ld), .a(0), .b(0), .o(o1), .done(done1), .sign_exe(sgnx1), .overflow(of1), .underflow(uf1));
178
fpDiv u2 (.clk(clk), .ce(1'b1), .ld(ld), .a(0), .b(0), .o(o2), .done(done2), .sign_exe(sgnx2), .overflow(of2), .underflow(uf2));
179
// 10/10
180
fpDiv u3 (.clk(clk), .ce(1'b1), .ld(ld), .a(32'h41200000), .b(32'h41200000), .done(done3), .o(o3), .sign_exe(sgnx2), .overflow(of2), .underflow(uf2));
181
// 21/-17
182
fpDiv u4 (.clk(clk), .ce(1'b1), .ld(ld), .a(32'h41a80000), .b(32'hc1880000), .done(done4), .o(o4), .sign_exe(sgnx2), .overflow(of2), .underflow(uf2));
183
// -17/-15
184
fpDiv u5 (.clk(clk), .ce(1'b1), .ld(ld), .a(32'hc1880000), .b(32'hc1700000), .done(done5), .o(o5), .sign_exe(sgnx2), .overflow(of2), .underflow(uf2));
185
 
186
fpNormalize u11 (clk, ce, 1'b0, o3, o11);
187
fpNormalize u12 (clk, ce, 1'b0, o4, o12);
188
fpNormalize u13 (clk, ce, 1'b0, o5, o13);
189
 
190
fpRound u21 (3'd1, o11, o21);         // zero for zero
191
fpRound u22 (3'd1, o12, o22); // 
192
fpRound u23 (3'd1, o13, o23); // 
193
 
194
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.