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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpDiv_tb.v] - Blame information for rev 85

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`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2018  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      fpDiv_tb.v
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//              - floating point divider test bench
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//      Floating Point Multiplier / Divider
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//
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//      This multiplier/divider handles denormalized numbers.
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//      The output format is of an internal expanded representation
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//      in preparation to be fed into a normalization unit, then
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//      rounding. Basically, it's the same as the regular format
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//      except the mantissa is doubled in size, the leading two
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//      bits of which are assumed to be whole bits.
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//
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//
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// ============================================================================
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module fpDiv_tb();
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reg rst;
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reg clk;
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reg [12:0] adr;
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reg [95:0] mem [0:8191];
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reg [95:0] memo [0:9000];
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reg [191:0] memd [0:8191];
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reg [191:0] memdo [0:9000];
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reg [31:0] a,b,a6,b6;
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reg [63:0] ad,bd;
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wire [31:0] a5,b5;
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wire [31:0] o;
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wire [63:0] od;
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reg ld;
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wire done;
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reg [3:0] state;
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initial begin
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        rst = 1'b0;
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        clk = 1'b0;
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        adr = 13'd0;
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        $readmemh("d:/cores5/ft64/v5/rtl/fpUnit/fpDiv_tv.txt", mem);
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        $readmemh("d:/cores5/ft64/v5/rtl/fpUnit/fpDiv_tvd.txt", memd);
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        #20 rst = 1'd1;
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        #50 rst = 1'd0;
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end
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always #10
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        clk = ~clk;
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always @(posedge clk)
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if (rst) begin
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        adr = 13'd0;
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        state <= 4'd4;
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end
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else
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begin
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        ld <= 1'b0;
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case(state)
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4'd1:
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        begin
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                a <= mem[adr][31: 0];
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                b <= mem[adr][63:32];
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                ad <= memd[adr][63:0];
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                bd <= memd[adr][127:64];
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                ld <= 1'b1;
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                state <= 4'd2;
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        end
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4'd2:
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                state <= 4'd3;
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4'd3:
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        if (done) begin
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                memo[adr] <= {o,b,a};
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                memdo[adr] <= {od,bd,ad};
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                adr <= adr + 4'd1;
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                if (adr==13'd8191) begin
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                        $writememh("d:/cores5/ft64/v5/rtl/fpUnit/fpDiv_tvo.txt", memo);
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                        $writememh("d:/cores5/ft64/v5/rtl/fpUnit/fpDiv_tvdo.txt", memdo);
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                        $finish;
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                end
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                state <= 4'd4;
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        end
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4'd4:   state <= 4'd5;
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4'd5:   state <= 1;
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endcase
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end
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fpDivnr #(32) u1 (rst, clk, 1'b1, ld, 1'b0, a, b, o, 3'b000);//, sign_exe, inf, overflow, underflow);
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fpDivnr #(64) u2 (rst, clk, 1'b1, ld, 1'b0, ad, bd, od, 3'b000, done);//, sign_exe, inf, overflow, underflow);
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endmodule

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