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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpLOOUnit.v] - Blame information for rev 39

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`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      fpLOOUnit.v
//              - single cycle latency floating point unit
//              - parameterized width
//              - IEEE 754 representation
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//      i2f - convert integer to floating point
//  f2i - convert floating point to integer
//
// ============================================================================
 
`define FLT1    4'h1
`define FLT2            4'h2
`define FTOI    5'h02
`define ITOF    5'h03
`define TRUNC           5'h15
`define NXTAFT  5'h0B
 
module fpLOOUnit
#(parameter WID=32)
(
        input clk,
        input ce,
        input [3:0] op4,
        input [4:0] func5,
        input [2:0] rm,
        input [WID-1:0] a,
        input [WID-1:0] b,
        output reg [WID-1:0] o,
        output done
);
`include "fpSize.sv"
 
wire [WID-1:0] i2f_o;
wire [WID-1:0] f2i_o;
wire [WID-1:0] trunc_o;
wire [WID-1:0] nxtaft_o;
 
delay1 u1 (
    .clk(clk),
    .ce(ce),
    .i((op4==`FLT1 && (func5==`ITOF||func5==`FTOI||func5==`TRUNC))||(op4==`FLT2 && (func5==`NXTAFT))),
    .o(done) );
i2f #(WID-4)  ui2fs (.clk(clk), .ce(ce), .rm(rm), .i(a[WID-1:4]), .o(i2f_o) );
f2i #(WID-4)  uf2is (.clk(clk), .ce(ce), .i(a[WID-1:4]), .o(f2i_o) );
fpTrunc #(WID) urho1 (.clk(clk), .ce(ce), .i(a), .o(trunc_o), .overflow());
fpNextAfter #(WID-4) una1 (.clk(clk), .ce(ce), .a(a[WID-1:4]), .b(b[WID-1:4]), .o(nxtaft_o));
 
always @*
        case (op4)
        `FLT1:
                case(func5)
                `ITOF:   o <= {i2f_o,4'h0};
                `FTOI:   o <= {f2i_o,4'h0};
                `TRUNC:  o <= trunc_o;
                default: o <= 0;
                endcase
        `FLT2:
                case(func5)
                `NXTAFT:        o <= {nxtaft_o,4'h0};
                default: o <= 0;
                endcase
        default:   o <= 0;
        endcase
 
endmodule

Line No.	Rev	Author	Line
1	9	robfinch	`timescale 1ns / 1ps
2			`// ============================================================================`
3			`// __`
4	26	robfinch	`// \\__/ o\ (C) 2006-2019 Robert Finch, Waterloo`
5	9	robfinch	`// \ __ / All rights reserved.`
6			`// \/_// robfinch<remove>@finitron.ca`
7			`// \|\|`
8			`//`
9			`// fpLOOUnit.v`
10			`// - single cycle latency floating point unit`
11			`// - parameterized width`
12			`// - IEEE 754 representation`
13			`//`
14			`//`
15			`// This source file is free software: you can redistribute it and/or modify`
16			`// it under the terms of the GNU Lesser General Public License as published`
17			`// by the Free Software Foundation, either version 3 of the License, or`
18			`// (at your option) any later version.`
19			`//`
20			`// This source file is distributed in the hope that it will be useful,`
21			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
22			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
23			`// GNU General Public License for more details.`
24			`//`
25			`// You should have received a copy of the GNU General Public License`
26			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
27			`//`
28			`// i2f - convert integer to floating point`
29			`// f2i - convert floating point to integer`
30			`//`
31			`// ============================================================================`
32
33	26	robfinch	`define FLT1 4'h1
34			`define FLT2 4'h2
35			`define FTOI 5'h02
36			`define ITOF 5'h03
37			`define TRUNC 5'h15
38			`define NXTAFT 5'h0B
39	9	robfinch
40			`module fpLOOUnit`
41			`#(parameter WID=32)`
42			`(`
43			`input clk,`
44			`input ce,`
45	26	robfinch	`input [3:0] op4,`
46			`input [4:0] func5,`
47			`input [2:0] rm,`
48	9	robfinch	`input [WID-1:0] a,`
49	26	robfinch	`input [WID-1:0] b,`
50	9	robfinch	`output reg [WID-1:0] o,`
51			`output done`
52			`);`
53	26	robfinch	`include "fpSize.sv"
54	9	robfinch
55			`wire [WID-1:0] i2f_o;`
56			`wire [WID-1:0] f2i_o;`
57	26	robfinch	`wire [WID-1:0] trunc_o;`
58			`wire [WID-1:0] nxtaft_o;`
59	9	robfinch
60	26	robfinch	`delay1 u1 (`
61			`.clk(clk),`
62			`.ce(ce),`
63			.i((op4==`FLT1 && (func5==`ITOF\|\|func5==`FTOI\|\|func5==`TRUNC))\|\|(op4==`FLT2 && (func5==`NXTAFT))),
64			`.o(done) );`
65			`i2f #(WID-4) ui2fs (.clk(clk), .ce(ce), .rm(rm), .i(a[WID-1:4]), .o(i2f_o) );`
66			`f2i #(WID-4) uf2is (.clk(clk), .ce(ce), .i(a[WID-1:4]), .o(f2i_o) );`
67			`fpTrunc #(WID) urho1 (.clk(clk), .ce(ce), .i(a), .o(trunc_o), .overflow());`
68			`fpNextAfter #(WID-4) una1 (.clk(clk), .ce(ce), .a(a[WID-1:4]), .b(b[WID-1:4]), .o(nxtaft_o));`
69	9	robfinch
70			`always @*`
71	26	robfinch	`case (op4)`
72			`FLT1:
73			`case(func5)`
74			`ITOF: o <= {i2f_o,4'h0};
75			`FTOI: o <= {f2i_o,4'h0};
76			`TRUNC: o <= trunc_o;
77			`default: o <= 0;`
78			`endcase`
79			`FLT2:
80			`case(func5)`
81			`NXTAFT: o <= {nxtaft_o,4'h0};
82			`default: o <= 0;`
83			`endcase`
84			`default: o <= 0;`
85			`endcase`
86	9	robfinch
87			`endmodule`

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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpLOOUnit.v] - Blame information for rev 39