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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpLOOUnit.v] - Blame information for rev 9

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Line No. Rev Author Line
1 9 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2016  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      fpLOOUnit.v
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//              - single cycle latency floating point unit
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//              - parameterized width
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//              - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//      i2f - convert integer to floating point
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//  f2i - convert floating point to integer
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//
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// ============================================================================
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`define FLOAT   6'h36
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`define FTOI    6'h02
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`define ITOF    6'h03
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module fpLOOUnit
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#(parameter WID=32)
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(
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        input clk,
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        input ce,
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        input [31:0] ir,
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        input [WID-1:0] a,
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        output reg [WID-1:0] o,
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        output done
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);
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localparam MSB = WID-1;
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localparam EMSB = WID==128 ? 14 :
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                  WID==96 ? 14 :
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                  WID==80 ? 14 :
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                  WID==64 ? 10 :
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                                  WID==52 ? 10 :
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                                  WID==48 ? 10 :
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                                  WID==44 ? 10 :
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                                  WID==42 ? 10 :
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                                  WID==40 ?  9 :
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                                  WID==32 ?  7 :
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                                  WID==24 ?  6 : 4;
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localparam FMSB = WID==128 ? 111 :
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                  WID==96 ? 79 :
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                  WID==80 ? 63 :
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                  WID==64 ? 51 :
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                                  WID==52 ? 39 :
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                                  WID==48 ? 35 :
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                                  WID==44 ? 31 :
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                                  WID==42 ? 29 :
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                                  WID==40 ? 28 :
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                                  WID==32 ? 22 :
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                                  WID==24 ? 15 : 9;
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wire [WID-1:0] i2f_o;
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wire [WID-1:0] f2i_o;
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wire [5:0] op = ir[5:0];
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wire [5:0] fn = ir[17:12];
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wire [2:0] rm = ir[26:24];
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wire [1:0] prec = ir[28:27];
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delay1 u1 (.clk(clk), .ce(ce), .i(op==`FLOAT && (fn==`ITOF||fn==`FTOI)), .o(done) );
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i2f #(WID)  ui2fs (.clk(clk), .ce(ce), .rm(rm), .i(a), .o(i2f_o) );
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f2i #(WID)  uf2is (.clk(clk), .ce(ce), .i(a), .o(f2i_o) );
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always @*
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        case (op)
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        `FLOAT:
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       case(fn)
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       `ITOF:   o <= i2f_o;
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       `FTOI:   o <= f2i_o;
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       default: o <= 0;
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       endcase
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    default:   o <= 0;
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    endcase
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endmodule

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