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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpNormalize.v] - Blame information for rev 10

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`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2018  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      fpNormalize.v
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//    - floating point normalization unit
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//    - two cycle latency
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//    - parameterized width
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//    - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//      This unit takes a floating point number in an intermediate
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// format and normalizes it. No normalization occurs
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// for NaN's or infinities. The unit has a two cycle latency.
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//
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// The mantissa is assumed to start with two whole bits on
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// the left. The remaining bits are fractional.
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//
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// The width of the incoming format is reduced via a generation
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// of sticky bit in place of the low order fractional bits.
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//
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// On an underflowed input, the incoming exponent is assumed
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// to be negative. A right shift is needed.
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// ============================================================================
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module fpNormalize(clk, ce, under, i, o);
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parameter WID = 128;
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localparam MSB = WID-1;
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localparam EMSB = WID==128 ? 14 :
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                  WID==96 ? 14 :
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                  WID==80 ? 14 :
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                  WID==64 ? 10 :
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                                  WID==52 ? 10 :
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                                  WID==48 ? 11 :
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                                  WID==44 ? 10 :
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                                  WID==42 ? 10 :
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                                  WID==40 ?  9 :
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                                  WID==32 ?  7 :
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                                  WID==24 ?  6 : 4;
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localparam FMSB = WID==128 ? 111 :
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                  WID==96 ? 79 :
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                  WID==80 ? 63 :
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                  WID==64 ? 51 :
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                                  WID==52 ? 39 :
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                                  WID==48 ? 34 :
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                                  WID==44 ? 31 :
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                                  WID==42 ? 29 :
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                                  WID==40 ? 28 :
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                                  WID==32 ? 22 :
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                                  WID==24 ? 15 : 9;
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localparam FX = (FMSB+2)*2-1;   // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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input clk;
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input ce;
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input under;
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input [EX:0] i;          // expanded format input
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output [WID+2:0] o;              // normalized output + guard, sticky and round bits, + 1 whole digit
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// variables
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wire so;
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wire so1 = i[EX];               // sign doesn't change
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// Since the there are *two* whole digits in the incoming format
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// the number of whole digits needs to be reduced. If the MSB is
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// set, then increment the exponent and no shift is needed.
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wire [EMSB:0] xo;
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wire [EMSB:0] xo1a = i[EX-1:FX+1];
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wire xInf = &xo1a & !under;
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wire incExp1 = !xInf & i[FX];
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wire [EMSB:0] xo1 = xo1a + incExp1;
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wire [EMSB:0] xo2;
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wire xInf1 = &xo1;
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// If infinity is reached then set the mantissa to zero
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wire gbit =  i[FMSB];
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wire rbit =  i[FMSB-1];
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wire sbit = |i[FMSB-2:0];
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// shift mantissa left by one to reduce to a single whole digit
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// if there is no exponent increment
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wire [FMSB+4:0] mo;
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wire [FMSB+4:0] mo1 = (xInf1 & incExp1) ? 0 :
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        incExp1 ? {i[FX:FMSB+2],gbit,rbit,sbit} :               // reduce mantissa size
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                         {i[FX-1:FMSB+1],gbit,rbit,sbit};       // reduce mantissa size
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wire [FMSB+3:0] mo2;
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wire [7:0] leadingZeros2;
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generate
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begin
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if (WID==32) begin
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
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assign leadingZeros2[7:6] = 2'b00;
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end
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else if (WID==128)
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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else if (WID==96)
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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else if (WID==80)
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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else if (WID==64)
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cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo1,8'h0}), .o(leadingZeros2) );
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end
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endgenerate
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// compensate for leadingZeros delay
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wire xInf2;
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delay1 #(EMSB+1) d2(.clk(clk), .ce(ce), .i(xo1), .o(xo2) );
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delay1 #(1)      d3(.clk(clk), .ce(ce), .i(xInf1), .o(xInf2) );
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// If the exponent underflowed, then the shift direction must be to the
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// right regardless of mantissa bits; the number is denormalized.
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// Otherwise the shift direction must be to the left.
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wire rightOrLeft2;      // 0=left,1=right
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delay1 #(1) d8(.clk(clk), .ce(ce), .i(under), .o(rightOrLeft2) );
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// Compute how much we want to decrement by
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wire [7:0] lshiftAmt2 = leadingZeros2 > xo2 ? xo2 : leadingZeros2;
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// compute amount to shift right
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// at infinity the exponent can't be incremented, so we can't shift right
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// otherwise it was an underflow situation so the exponent was negative
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// shift amount needs to be negated for shift register
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wire [7:0] rshiftAmt2 = xInf2 ? 0 : (($unsigned(-xo2) > $unsigned(FMSB+3)) ? FMSB+4 : -xo2);//FMSB+4+xo2; // xo2 is negative !
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// sign
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// the output sign is the same as the input sign
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delay1 #(1)      d7(.clk(clk), .ce(ce), .i(so1), .o(so) );
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// exponent
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//      always @(posedge clk)
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//              if (ce)
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assign xo =
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                xInf2 ? xo2 :           // an infinite exponent is either a NaN or infinity; no need to change
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                rightOrLeft2 ? 0 :       // on a right shift, the exponent was negative, it's being made to zero
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                xo2 - lshiftAmt2;       // on a left shift, the exponent can't be decremented below zero
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// mantissa
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delay1 #(FMSB+5) d4(.clk(clk), .ce(ce), .i(mo1), .o(mo2) );
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wire [FMSB+3:0] mo2a;
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//shiftAndMask #(FMSB+4) u1 (.op({rightOrLeft2,1'b0}), .a(mo2), .b(rightOrLeft2 ? lshiftAmt2 : rshiftAmt2), .mb(6'd0), .me(FMSB+3), .o(mo2a) );
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//      always @(posedge clk)
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//              if (ce)
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assign mo = rightOrLeft2 ? (mo2 >> rshiftAmt2) : (mo2 << lshiftAmt2);
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//always @(posedge clk)
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//      $display("%c xo2=%d -xo2=%d rshift=%d >%d %d", rightOrLeft2 ? "r" : "l",xo2, -xo2, rshiftAmt2,($unsigned(-xo2) > $unsigned(FMSB+3)),FMSB+3);
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assign o = {so,xo,mo[FMSB+4:1]};
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endmodule
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