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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpSigmoid.v] - Blame information for rev 23

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// ============================================================================
//        __
//   \\__/ o\    (C) 2017-2019  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      sigmoid.v
//              - perform sigmoid function
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
// This module returns the sigmoid of a number using a lookup table.
// -1.0 or +1.0 is returned for entries outside of the range -8.0 to +8.0
//                                                                          
// ToTo: check pipelining of values
// ============================================================================
 
`define ONE80                                   80'h3FFF0000000000000000
`define EIGHT80                         80'h40020000000000000000
`define FIVETWELVE80    80'h40080000000000000000
`define ONE64                                   64'h3FF0000000000000
`define EIGHT64                         64'h4020000000000000
`define FIVETWELVE64    64'h4080000000000000
`define ONE40                                   40'h3FE0000000
`define EIGHT40                         40'h4040000000
`define ONE32                                   32'h7F000000
`define EIGHT32                         32'h42000000
`define FIVETWELVE32    32'h48000000
 
module fpSigmoid(clk, ce, a, o);
parameter WID = 128;
localparam MSB = WID-1;
localparam EMSB = WID==128 ? 14 :
                  WID==96 ? 14 :
                  WID==80 ? 14 :
                  WID==64 ? 10 :
                                  WID==52 ? 10 :
                                  WID==48 ? 11 :
                                  WID==44 ? 10 :
                                  WID==42 ? 10 :
                                  WID==40 ?  9 :
                                  WID==32 ?  7 :
                                  WID==24 ?  6 : 4;
localparam FMSB = WID==128 ? 111 :
                  WID==96 ? 79 :
                  WID==80 ? 63 :
                  WID==64 ? 51 :
                                  WID==52 ? 39 :
                                  WID==48 ? 34 :
                                  WID==44 ? 31 :
                                  WID==42 ? 29 :
                                  WID==40 ? 28 :
                                  WID==32 ? 22 :
                                  WID==24 ? 15 : 9;
input clk;
input ce;
input [WID-1:0] a;
output reg [WID-1:0] o;
 
wire [4:0] cmp1_o;
reg [4:0] cmp2_o;
 
// Just the mantissa is stored in the table to economize on the storate.
// The exponent is always the same value (0x3ff). Only the top 32 bits of
// the mantissa are stored.
(* ram_style="block" *)
reg [31:0] SigmoidLUT [0:1023];
 
// Check if the input is in the range (-8 to +8)
// We take the absolute value by trimming off the sign bit.
generate begin : ext
if (WID==80)
fp_cmp_unit #(WID) u1 (.a(a & 80'h7FFFFFFFFFFFFFFFFFFF), .b(`EIGHT80), .o(cmp1_o), .nanx() );
else if (WID==64)
fp_cmp_unit #(WID) u1 (.a(a & 64'h7FFFFFFFFFFFFFFF), .b(`EIGHT64), .o(cmp1_o), .nanx() );
else if (WID==40)
fp_cmp_unit #(WID) u1 (.a(a & 40'h7FFFFFFFFF), .b(`EIGHT40), .o(cmp1_o), .nanx() );
else if (WID==32)
fp_cmp_unit #(WID) u1 (.a(a & 32'h7FFFFFFF), .b(`EIGHT32), .o(cmp1_o), .nanx() );
else begin
        always @*
        begin
                $display("Sigmoid: unsupported width.");
                $stop;
        end
end
end
endgenerate
 
initial begin
`include "D:\Cores6\rtfItanium\v1\rtl\fpUnit\SigTbl.ver"
end
 
// Quickly multiply number by 64 (it is in range -8 to 8) then convert to integer to get
// table index = add 6 to exponent then convert to integer
wire sa;
wire [EMSB:0] xa;
wire [FMSB:0] ma;
fpDecomp #(WID) u1 (.i(a), .sgn(sa), .exp(xa), .man(ma), .fract(), .xz(), .vz(), .xinf(), .inf(), .nan() );
 
reg [9:0] lutadr;
wire [5:0] lzcnt;
wire [WID-1:0] a1;
wire [WID-1:0] i1, i2;
wire [EMSB:0] xa1 = xa + 4'd6;
assign a1 = {sa,xa1,ma};        // we know the exponent won't overflow
wire [31:0] man32a = SigmoidLUT[lutadr];
wire [31:0] man32b = lutadr==10'h3ff ? man32a : SigmoidLUT[lutadr+1];
wire [31:0] man32;
wire [79:0] sig80;
generate begin : la
if (WID >= 40) begin
wire [15:0] eps = ma[FMSB-10:FMSB-10-15];
wire [47:0] p = (man32b - man32a) * eps;
assign man32 = man32a + (p >> 26);
cntlz32 u3 (man32,lzcnt);
end
else if (WID==32) begin
wire [12:0] eps = ma[FMSB-10:0];
wire [43:0] p = (man32b - man32a) * eps;
assign man32 = man32a + (p >> 26);
cntlz32 u3 (man32,lzcnt);
end
end
endgenerate
 
wire [31:0] man32s = man32 << (lzcnt + 2'd1);    // +1 to hide leading one
 
// Convert to integer
f2i #(WID) u2
(
  .clk(clk),
  .ce(1'b1),
  .i(a1),
  .o(i2)
);
assign i1 = i2 + 512;
 
always @(posedge clk)
  if (ce) cmp2_o <= cmp1_o;
 
// We know the integer is in range 0 to 1023
always @(posedge clk)
  if(ce) lutadr <= i1[9:0];
reg sa1,sa2;
always @(posedge clk)
if (ce) sa1 <= a[WID-1];
always @(posedge clk)
if (ce) sa2 <= sa1;
 
generate begin : ooo
if (WID==80) begin
wire [14:0] ex1 = 15'h3ffe - lzcnt;
always @(posedge clk)
if (ce) begin
        if (cmp2_o[1])  // abs(a) less than 8 ?
          o <= {1'b0,ex1,man32s[31:0],32'd0};
        else
          o <= sa1 ? 80'h0 : `ONE80;
end
end
else if (WID==64) begin
wire [10:0] ex1 = 11'h3fe - lzcnt;
always @(posedge clk)
if (ce) begin
        if (cmp2_o[1])  // abs(a) less than 8 ?
          o <= {1'b0,ex1,man32s[31:0],20'd0};
        else
          o <= sa1 ? 64'h0 : `ONE64;
end
end
else if (WID==40) begin
wire [9:0] ex1 = 10'h1fe - lzcnt;
always @(posedge clk)
if (ce) begin
        if (cmp2_o[1])  // abs(a) less than 8 ?
          o <= {1'b0,ex1,man32s[31:3]};
        else
          o <= sa1 ? 40'h0 : `ONE40;
end
end
else if (WID==32) begin
wire [7:0] ex1 = 8'h7e - lzcnt;
always @(posedge clk)
if (ce) begin
        if (cmp2_o[1])  // abs(a) less than 8 ?
          o <= {1'b0,ex1,man32s[31:9]};
        else
          o <= sa1 ? 32'h0 : `ONE32;
end
end
end
endgenerate
 
endmodule

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Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpSigmoid.v] - Blame information for rev 23

Line No.	Rev	Author	Line
1	18	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2017-2019 Robert Finch, Waterloo`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@finitron.ca`
6			`// \|\|`
7			`//`
8			`// sigmoid.v`
9			`// - perform sigmoid function`
10			`//`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`//`
26			`// This module returns the sigmoid of a number using a lookup table.`
27			`// -1.0 or +1.0 is returned for entries outside of the range -8.0 to +8.0`
28			`//`
29			`// ToTo: check pipelining of values`
30			`// ============================================================================`
31
32			`define ONE80 80'h3FFF0000000000000000
33			`define EIGHT80 80'h40020000000000000000
34			`define FIVETWELVE80 80'h40080000000000000000
35			`define ONE64 64'h3FF0000000000000
36			`define EIGHT64 64'h4020000000000000
37			`define FIVETWELVE64 64'h4080000000000000
38			`define ONE40 40'h3FE0000000
39			`define EIGHT40 40'h4040000000
40			`define ONE32 32'h7F000000
41			`define EIGHT32 32'h42000000
42			`define FIVETWELVE32 32'h48000000
43
44			`module fpSigmoid(clk, ce, a, o);`
45			`parameter WID = 128;`
46			`localparam MSB = WID-1;`
47			`localparam EMSB = WID==128 ? 14 :`
48			`WID==96 ? 14 :`
49			`WID==80 ? 14 :`
50			`WID==64 ? 10 :`
51			`WID==52 ? 10 :`
52			`WID==48 ? 11 :`
53			`WID==44 ? 10 :`
54			`WID==42 ? 10 :`
55			`WID==40 ? 9 :`
56			`WID==32 ? 7 :`
57			`WID==24 ? 6 : 4;`
58			`localparam FMSB = WID==128 ? 111 :`
59			`WID==96 ? 79 :`
60			`WID==80 ? 63 :`
61			`WID==64 ? 51 :`
62			`WID==52 ? 39 :`
63			`WID==48 ? 34 :`
64			`WID==44 ? 31 :`
65			`WID==42 ? 29 :`
66			`WID==40 ? 28 :`
67			`WID==32 ? 22 :`
68			`WID==24 ? 15 : 9;`
69			`input clk;`
70			`input ce;`
71			`input [WID-1:0] a;`
72			`output reg [WID-1:0] o;`
73
74			`wire [4:0] cmp1_o;`
75			`reg [4:0] cmp2_o;`
76
77			`// Just the mantissa is stored in the table to economize on the storate.`
78			`// The exponent is always the same value (0x3ff). Only the top 32 bits of`
79			`// the mantissa are stored.`
80			`(* ram_style="block" *)`
81			`reg [31:0] SigmoidLUT [0:1023];`
82
83			`// Check if the input is in the range (-8 to +8)`
84			`// We take the absolute value by trimming off the sign bit.`
85			`generate begin : ext`
86			`if (WID==80)`
87			fp_cmp_unit #(WID) u1 (.a(a & 80'h7FFFFFFFFFFFFFFFFFFF), .b(`EIGHT80), .o(cmp1_o), .nanx() );
88			`else if (WID==64)`
89			fp_cmp_unit #(WID) u1 (.a(a & 64'h7FFFFFFFFFFFFFFF), .b(`EIGHT64), .o(cmp1_o), .nanx() );
90			`else if (WID==40)`
91			fp_cmp_unit #(WID) u1 (.a(a & 40'h7FFFFFFFFF), .b(`EIGHT40), .o(cmp1_o), .nanx() );
92			`else if (WID==32)`
93			fp_cmp_unit #(WID) u1 (.a(a & 32'h7FFFFFFF), .b(`EIGHT32), .o(cmp1_o), .nanx() );
94			`else begin`
95			`always @*`
96			`begin`
97			`$display("Sigmoid: unsupported width.");`
98			`$stop;`
99			`end`
100			`end`
101			`end`
102			`endgenerate`
103
104			`initial begin`
105			`include "D:\Cores6\rtfItanium\v1\rtl\fpUnit\SigTbl.ver"
106			`end`
107
108			`// Quickly multiply number by 64 (it is in range -8 to 8) then convert to integer to get`
109			`// table index = add 6 to exponent then convert to integer`
110			`wire sa;`
111			`wire [EMSB:0] xa;`
112			`wire [FMSB:0] ma;`
113			`fpDecomp #(WID) u1 (.i(a), .sgn(sa), .exp(xa), .man(ma), .fract(), .xz(), .vz(), .xinf(), .inf(), .nan() );`
114
115			`reg [9:0] lutadr;`
116			`wire [5:0] lzcnt;`
117			`wire [WID-1:0] a1;`
118			`wire [WID-1:0] i1, i2;`
119			`wire [EMSB:0] xa1 = xa + 4'd6;`
120			`assign a1 = {sa,xa1,ma}; // we know the exponent won't overflow`
121			`wire [31:0] man32a = SigmoidLUT[lutadr];`
122			`wire [31:0] man32b = lutadr==10'h3ff ? man32a : SigmoidLUT[lutadr+1];`
123			`wire [31:0] man32;`
124			`wire [79:0] sig80;`
125			`generate begin : la`
126			`if (WID >= 40) begin`
127			`wire [15:0] eps = ma[FMSB-10:FMSB-10-15];`
128			`wire [47:0] p = (man32b - man32a) * eps;`
129			`assign man32 = man32a + (p >> 26);`
130			`cntlz32 u3 (man32,lzcnt);`
131			`end`
132			`else if (WID==32) begin`
133			`wire [12:0] eps = ma[FMSB-10:0];`
134			`wire [43:0] p = (man32b - man32a) * eps;`
135			`assign man32 = man32a + (p >> 26);`
136			`cntlz32 u3 (man32,lzcnt);`
137			`end`
138			`end`
139			`endgenerate`
140
141			`wire [31:0] man32s = man32 << (lzcnt + 2'd1); // +1 to hide leading one`
142
143			`// Convert to integer`
144			`f2i #(WID) u2`
145			`(`
146			`.clk(clk),`
147			`.ce(1'b1),`
148			`.i(a1),`
149			`.o(i2)`
150			`);`
151			`assign i1 = i2 + 512;`
152
153			`always @(posedge clk)`
154			`if (ce) cmp2_o <= cmp1_o;`
155
156			`// We know the integer is in range 0 to 1023`
157			`always @(posedge clk)`
158			`if(ce) lutadr <= i1[9:0];`
159			`reg sa1,sa2;`
160			`always @(posedge clk)`
161			`if (ce) sa1 <= a[WID-1];`
162			`always @(posedge clk)`
163			`if (ce) sa2 <= sa1;`
164
165			`generate begin : ooo`
166			`if (WID==80) begin`
167			`wire [14:0] ex1 = 15'h3ffe - lzcnt;`
168			`always @(posedge clk)`
169			`if (ce) begin`
170			`if (cmp2_o[1]) // abs(a) less than 8 ?`
171			`o <= {1'b0,ex1,man32s[31:0],32'd0};`
172			`else`
173			o <= sa1 ? 80'h0 : `ONE80;
174			`end`
175			`end`
176			`else if (WID==64) begin`
177			`wire [10:0] ex1 = 11'h3fe - lzcnt;`
178			`always @(posedge clk)`
179			`if (ce) begin`
180			`if (cmp2_o[1]) // abs(a) less than 8 ?`
181			`o <= {1'b0,ex1,man32s[31:0],20'd0};`
182			`else`
183			o <= sa1 ? 64'h0 : `ONE64;
184			`end`
185			`end`
186			`else if (WID==40) begin`
187			`wire [9:0] ex1 = 10'h1fe - lzcnt;`
188			`always @(posedge clk)`
189			`if (ce) begin`
190			`if (cmp2_o[1]) // abs(a) less than 8 ?`
191			`o <= {1'b0,ex1,man32s[31:3]};`
192			`else`
193			o <= sa1 ? 40'h0 : `ONE40;
194			`end`
195			`end`
196			`else if (WID==32) begin`
197			`wire [7:0] ex1 = 8'h7e - lzcnt;`
198			`always @(posedge clk)`
199			`if (ce) begin`
200			`if (cmp2_o[1]) // abs(a) less than 8 ?`
201			`o <= {1'b0,ex1,man32s[31:9]};`
202			`else`
203			o <= sa1 ? 32'h0 : `ONE32;
204			`end`
205			`end`
206			`end`
207			`endgenerate`
208
209			`endmodule`