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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpTrunc.sv] - Blame information for rev 63

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1 21 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      fpTrunc.v
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//              - convert floating point to integer (chop off fractional bits)
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//              - single cycle latency floating point unit
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//              - parameterized width
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//              - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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//
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// ============================================================================
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module fpTrunc
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#(      parameter WID = 32)
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(
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        input clk,
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        input ce,
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        input [WID-1:0] i,
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        output reg [WID-1:0] o,
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        output overflow
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);
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`include "fpSize.sv"
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integer n;
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wire [MSB:0] maxInt  = {MSB{1'b1}};             // maximum unsigned integer value
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wire [EMSB:0] zeroXp = {EMSB{1'b1}};    // simple constant - value of exp for zero
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// Decompose fp value
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reg sgn;                                                                        // sign
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reg [EMSB:0] exp;
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reg [FMSB:0] man;
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reg [FMSB:0] mask;
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wire [7:0] shamt = FMSB - (exp - zeroXp);
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always @*
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for (n = 0; n <= FMSB; n = n +1)
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        mask[n] = (n > shamt);
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always @*
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        sgn = i[MSB];
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always @*
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        exp = i[MSB-1:FMSB+1];
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always @*
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        if (exp > zeroXp + FMSB)
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                man = i[FMSB:0];
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        else
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                man = i[FMSB:0] & mask;
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always @(posedge clk)
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        if (ce) begin
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                if (exp < zeroXp)
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                        o <= 1'd0;
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                else
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                        o <= {sgn,exp,man};
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        end
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endmodule

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