URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog/] [lib/] [cntlz.sv] - Blame information for rev 63

Details | Compare with Previous | View Log


`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2006-2022  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//       ||
//
//      cntlz.v
//      - count number of leading zeros in a byte
//      - count number of leading ones in a byte
//      - simple fast approach - lookup table
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
//    list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
//    contributors may be used to endorse or promote products derived from
//    this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
module cntlz8(
        input [7:0] i,
        output reg [3:0] o
);
 
        always_comb
                case (i)
                8'b00000000:    o = 8;
                8'b00000001:    o = 7;
                8'b00000010:    o = 6;
                8'b00000011:    o = 6;
                8'b00000100:    o = 5;
                8'b00000101:    o = 5;
                8'b00000110:    o = 5;
                8'b00000111:    o = 5;
                8'b00001000:    o = 4;
                8'b00001001:    o = 4;
                8'b00001010:    o = 4;
                8'b00001011:    o = 4;
                8'b00001100:    o = 4;
                8'b00001101:    o = 4;
                8'b00001110:    o = 4;
                8'b00001111:    o = 4;
 
                8'b00010000:    o = 3;
                8'b00010001:    o = 3;
                8'b00010010:    o = 3;
                8'b00010011:    o = 3;
                8'b00010100:    o = 3;
                8'b00010101:    o = 3;
                8'b00010110:    o = 3;
                8'b00010111:    o = 3;
                8'b00011000:    o = 3;
                8'b00011001:    o = 3;
                8'b00011010:    o = 3;
                8'b00011011:    o = 3;
                8'b00011100:    o = 3;
                8'b00011101:    o = 3;
                8'b00011110:    o = 3;
                8'b00011111:    o = 3;
 
                8'b00100000:    o = 2;
                8'b00100001:    o = 2;
                8'b00100010:    o = 2;
                8'b00100011:    o = 2;
                8'b00100100:    o = 2;
                8'b00100101:    o = 2;
                8'b00100110:    o = 2;
                8'b00100111:    o = 2;
                8'b00101000:    o = 2;
                8'b00101001:    o = 2;
                8'b00101010:    o = 2;
                8'b00101011:    o = 2;
                8'b00101100:    o = 2;
                8'b00101101:    o = 2;
                8'b00101110:    o = 2;
                8'b00101111:    o = 2;
 
                8'b00110000:    o = 2;
                8'b00110001:    o = 2;
                8'b00110010:    o = 2;
                8'b00110011:    o = 2;
                8'b00110100:    o = 2;
                8'b00110101:    o = 2;
                8'b00110110:    o = 2;
                8'b00110111:    o = 2;
                8'b00111000:    o = 2;
                8'b00111001:    o = 2;
                8'b00111010:    o = 2;
                8'b00111011:    o = 2;
                8'b00111100:    o = 2;
                8'b00111101:    o = 2;
                8'b00111110:    o = 2;
                8'b00111111:    o = 2;
 
                // 44 - 1
                8'b01000000:    o = 1;
                8'b01000001:    o = 1;
                8'b01000010:    o = 1;
                8'b01000011:    o = 1;
                8'b01000100:    o = 1;
                8'b01000101:    o = 1;
                8'b01000110:    o = 1;
                8'b01000111:    o = 1;
                8'b01001000:    o = 1;
                8'b01001001:    o = 1;
                8'b01001010:    o = 1;
                8'b01001011:    o = 1;
                8'b01001100:    o = 1;
                8'b01001101:    o = 1;
                8'b01001110:    o = 1;
                8'b01001111:    o = 1;
 
                8'b01010000:    o = 1;
                8'b01010001:    o = 1;
                8'b01010010:    o = 1;
                8'b01010011:    o = 1;
                8'b01010100:    o = 1;
                8'b01010101:    o = 1;
                8'b01010110:    o = 1;
                8'b01010111:    o = 1;
                8'b01011000:    o = 1;
                8'b01011001:    o = 1;
                8'b01011010:    o = 1;
                8'b01011011:    o = 1;
                8'b01011100:    o = 1;
                8'b01011101:    o = 1;
                8'b01011110:    o = 1;
                8'b01011111:    o = 1;
 
                8'b01100000:    o = 1;
                8'b01100001:    o = 1;
                8'b01100010:    o = 1;
                8'b01100011:    o = 1;
                8'b01100100:    o = 1;
                8'b01100101:    o = 1;
                8'b01100110:    o = 1;
                8'b01100111:    o = 1;
                8'b01101000:    o = 1;
                8'b01101001:    o = 1;
                8'b01101010:    o = 1;
                8'b01101011:    o = 1;
                8'b01101100:    o = 1;
                8'b01101101:    o = 1;
                8'b01101110:    o = 1;
                8'b01101111:    o = 1;
 
                8'b01110000:    o = 1;
                8'b01110001:    o = 1;
                8'b01110010:    o = 1;
                8'b01110011:    o = 1;
                8'b01110100:    o = 1;
                8'b01110101:    o = 1;
                8'b01110110:    o = 1;
                8'b01110111:    o = 1;
                8'b01111000:    o = 1;
                8'b01111001:    o = 1;
                8'b01111010:    o = 1;
                8'b01111011:    o = 1;
                8'b01111100:    o = 1;
                8'b01111101:    o = 1;
                8'b01111110:    o = 1;
                8'b01111111:    o = 1;
 
                //  - 2
                8'b10000000:    o = 0;
                8'b10000001:    o = 0;
                8'b10000010:    o = 0;
                8'b10000011:    o = 0;
                8'b10000100:    o = 0;
                8'b10000101:    o = 0;
                8'b10000110:    o = 0;
                8'b10000111:    o = 0;
                8'b10001000:    o = 0;
                8'b10001001:    o = 0;
                8'b10001010:    o = 0;
                8'b10001011:    o = 0;
                8'b10001100:    o = 0;
                8'b10001101:    o = 0;
                8'b10001110:    o = 0;
                8'b10001111:    o = 0;
 
                8'b10010000:    o = 0;
                8'b10010001:    o = 0;
                8'b10010010:    o = 0;
                8'b10010011:    o = 0;
                8'b10010100:    o = 0;
                8'b10010101:    o = 0;
                8'b10010110:    o = 0;
                8'b10010111:    o = 0;
                8'b10011000:    o = 0;
                8'b10011001:    o = 0;
                8'b10011010:    o = 0;
                8'b10011011:    o = 0;
                8'b10011100:    o = 0;
                8'b10011101:    o = 0;
                8'b10011110:    o = 0;
                8'b10011111:    o = 0;
 
                8'b10100000:    o = 0;
                8'b10100001:    o = 0;
                8'b10100010:    o = 0;
                8'b10100011:    o = 0;
                8'b10100100:    o = 0;
                8'b10100101:    o = 0;
                8'b10100110:    o = 0;
                8'b10100111:    o = 0;
                8'b10101000:    o = 0;
                8'b10101001:    o = 0;
                8'b10101010:    o = 0;
                8'b10101011:    o = 0;
                8'b10101100:    o = 0;
                8'b10101101:    o = 0;
                8'b10101110:    o = 0;
                8'b10101111:    o = 0;
 
                8'b10110000:    o = 0;
                8'b10110001:    o = 0;
                8'b10110010:    o = 0;
                8'b10110011:    o = 0;
                8'b10110100:    o = 0;
                8'b10110101:    o = 0;
                8'b10110110:    o = 0;
                8'b10110111:    o = 0;
                8'b10111000:    o = 0;
                8'b10111001:    o = 0;
                8'b10111010:    o = 0;
                8'b10111011:    o = 0;
                8'b10111100:    o = 0;
                8'b10111101:    o = 0;
                8'b10111110:    o = 0;
                8'b10111111:    o = 0;
 
                // 44 - 3
                8'b11000000:    o = 0;
                8'b11000001:    o = 0;
                8'b11000010:    o = 0;
                8'b11000011:    o = 0;
                8'b11000100:    o = 0;
                8'b11000101:    o = 0;
                8'b11000110:    o = 0;
                8'b11000111:    o = 0;
                8'b11001000:    o = 0;
                8'b11001001:    o = 0;
                8'b11001010:    o = 0;
                8'b11001011:    o = 0;
                8'b11001100:    o = 0;
                8'b11001101:    o = 0;
                8'b11001110:    o = 0;
                8'b11001111:    o = 0;
 
                8'b11010000:    o = 0;
                8'b11010001:    o = 0;
                8'b11010010:    o = 0;
                8'b11010011:    o = 0;
                8'b11010100:    o = 0;
                8'b11010101:    o = 0;
                8'b11010110:    o = 0;
                8'b11010111:    o = 0;
                8'b11011000:    o = 0;
                8'b11011001:    o = 0;
                8'b11011010:    o = 0;
                8'b11011011:    o = 0;
                8'b11011100:    o = 0;
                8'b11011101:    o = 0;
                8'b11011110:    o = 0;
                8'b11011111:    o = 0;
 
                8'b11100000:    o = 0;
                8'b11100001:    o = 0;
                8'b11100010:    o = 0;
                8'b11100011:    o = 0;
                8'b11100100:    o = 0;
                8'b11100101:    o = 0;
                8'b11100110:    o = 0;
                8'b11100111:    o = 0;
                8'b11101000:    o = 0;
                8'b11101001:    o = 0;
                8'b11101010:    o = 0;
                8'b11101011:    o = 0;
                8'b11101100:    o = 0;
                8'b11101101:    o = 0;
                8'b11101110:    o = 0;
                8'b11101111:    o = 0;
 
                8'b11110000:    o = 0;
                8'b11110001:    o = 0;
                8'b11110010:    o = 0;
                8'b11110011:    o = 0;
                8'b11110100:    o = 0;
                8'b11110101:    o = 0;
                8'b11110110:    o = 0;
                8'b11110111:    o = 0;
                8'b11111000:    o = 0;
                8'b11111001:    o = 0;
                8'b11111010:    o = 0;
                8'b11111011:    o = 0;
                8'b11111100:    o = 0;
                8'b11111101:    o = 0;
                8'b11111110:    o = 0;
                8'b11111111:    o = 0;
 
                endcase
 
 
endmodule
 
 
module cntlz16(
        input [15:0] i,
        output [4:0] o
);
 
        wire [3:0] cnt1, cnt2;
 
        cntlz8 u1 (i[ 7:0],cnt1);
        cntlz8 u2 (i[15:8],cnt2);
 
        assign o = cnt2[3] ? cnt1 + 4'h8 : cnt2;
 
endmodule
 
 
// 39 slices / 67 LUTs / 19.3ns
module cntlz24(
        input [23:0] i,
        output [4:0] o
);
 
        wire [3:0] cnt1, cnt2, cnt3;
 
        // cntlz8 results in faster result than cntlz16
        cntlz8 u1 (i[ 7: 0],cnt1);
        cntlz8 u2 (i[15: 8],cnt2);
        cntlz8 u3 (i[23:16],cnt3);
 
        assign o =
                !cnt3[3] ? cnt3 :
                !cnt2[3] ? cnt2 + 5'd8 :
                 cnt1 + 5'd16;
 
endmodule
 
// 39 slices / 67 LUTs / 19.3ns
module cntlz32(
        input [31:0] i,
        output [5:0] o
);
 
        wire [3:0] cnt1, cnt2, cnt3, cnt4;
 
        // cntlz8 results in faster result than cntlz16
        cntlz8 u1 (i[ 7: 0],cnt1);
        cntlz8 u2 (i[15: 8],cnt2);
        cntlz8 u3 (i[23:16],cnt3);
        cntlz8 u4 (i[31:24],cnt4);
 
        assign o =
                !cnt4[3] ? cnt4 :
                !cnt3[3] ? cnt3 + 6'd8 :
                !cnt2[3] ? cnt2 + 6'd16 :
                 cnt1 + 6'd24;
 
endmodule
 
 
// 88 slices / 154 LUTs / 22.5 ns
module cntlz48(
        input [47:0] i,
        output [5:0] o
);
 
        wire [4:0] cnt1, cnt2, cnt3;
 
        cntlz16 u1 (i[15: 0],cnt1);
        cntlz16 u2 (i[31:16],cnt2);
        cntlz16 u3 (i[47:32],cnt3);
 
        assign o =
                !cnt3[4] ? cnt3 :
                !cnt2[4] ? cnt2 + 7'd16 :
                 cnt1 + 7'd32;
 
endmodule
 
 
// 88 slices / 154 LUTs / 22.5 ns
module cntlz64(
        input [63:0] i,
        output [6:0] o
);
 
        wire [4:0] cnt1, cnt2, cnt3, cnt4;
 
        cntlz16 u1 (i[15: 0],cnt1);
        cntlz16 u2 (i[31:16],cnt2);
        cntlz16 u3 (i[47:32],cnt3);
        cntlz16 u4 (i[63:48],cnt4);
 
        assign o =
                !cnt4[4] ? cnt4 :
                !cnt3[4] ? cnt3 + 7'd16 :
                !cnt2[4] ? cnt2 + 7'd32 :
                 cnt1 + 7'd48;
 
endmodule
 
 
module cntlz80(
        input [79:0] i,
        output [6:0] o
);
 
    wire [4:0] cnt3;
        wire [5:0] cnt1, cnt2;
 
        cntlz32 u1 (i[31: 0],cnt1);
        cntlz32 u2 (i[63:32],cnt2);
        cntlz16 u3 (i[79:64],cnt3);
 
        assign o =
                !cnt3[4] ? {2'b0,cnt3} :
                !cnt2[5] ? {1'b0,cnt2} + 8'd16 :
                 {1'b0,cnt1} + 7'd48;
 
endmodule
 
 
module cntlz96(
        input [95:0] i,
        output [7:0] o
);
 
        wire [5:0] cnt1, cnt2, cnt3;
 
        cntlz32 u1 (i[31: 0],cnt1);
        cntlz32 u2 (i[63:32],cnt2);
        cntlz32 u3 (i[95:64],cnt3);
 
        assign o =
                !cnt3[5] ? cnt3 :
                !cnt2[5] ? cnt2 + 8'd32 :
                 cnt1 + 8'd64;
 
endmodule
 
 
module cntlz128(
        input [127:0] i,
        output [7:0] o
);
 
        wire [5:0] cnt1, cnt2, cnt3, cnt4;
 
        cntlz32 u1 (i[31: 0],cnt1);
        cntlz32 u2 (i[63:32],cnt2);
        cntlz32 u3 (i[95:64],cnt3);
        cntlz32 u4 (i[127:96],cnt4);
 
        assign o =
                !cnt4[5] ? cnt4 :
                !cnt3[5] ? cnt3 + 8'd32 :
                !cnt2[5] ? cnt2 + 8'd64 :
                 cnt1 + 8'd96;
 
endmodule
 
 
module cntlz192(
        input [191:0] i,
        output [7:0] o
);
 
        wire [5:0] cnt1, cnt2, cnt3, cnt4, cnt5, cnt6;
 
        cntlz32 u1 (i[31: 0],cnt1);
        cntlz32 u2 (i[63:32],cnt2);
        cntlz32 u3 (i[95:64],cnt3);
        cntlz32 u4 (i[127:96],cnt4);
        cntlz32 u5 (i[159:128],cnt5);
        cntlz32 u6 (i[191:160],cnt6);
 
        assign o =
                !cnt6[5] ? cnt6 :
                !cnt5[5] ? cnt5 + 8'd32 :
                !cnt4[5] ? cnt4 + 8'd64:
                !cnt3[5] ? cnt3 + 8'd96 :
                !cnt2[5] ? cnt2 + 8'd128 :
                 cnt1 + 8'd160;
 
endmodule
 
 
module cntlz32Reg(
        input clk,
        input ce,
        input [31:0] i,
        output reg [5:0] o
);
 
        wire [5:0] o1;
        cntlz32 u1 (i,o1);
        always @(posedge clk)
                if (ce) o <= o1;
 
endmodule
 
 
module cntlz64Reg(
        input clk,
        input ce,
        input [63:0] i,
        output reg [6:0] o
);
 
        wire [6:0] o1;
        cntlz64 u1 (i,o1);
        always @(posedge clk)
                if (ce) o <= o1;
 
endmodule
 
module cntlz80Reg(
        input clk,
        input ce,
        input [79:0] i,
        output reg [6:0] o
);
 
        wire [6:0] o1;
        cntlz80 u1 (i,o1);
        always @(posedge clk)
                if (ce) o <= o1;
 
endmodule
 
module cntlz96Reg(
        input clk,
        input ce,
        input [95:0] i,
        output reg [7:0] o
);
 
        wire [7:0] o1;
        cntlz96 u1 (i,o1);
        always @(posedge clk)
                if (ce) o <= o1;
 
endmodule
 
module cntlz128Reg(
        input clk,
        input ce,
        input [127:0] i,
        output reg [7:0] o
);
 
        wire [7:0] o1;
        cntlz128 u1 (i,o1);
        always @(posedge clk)
                if (ce) o <= o1;
 
endmodule
 
module cntlz192Reg(
        input clk,
        input ce,
        input [191:0] i,
        output reg [7:0] o
);
 
        wire [7:0] o1;
        cntlz192 u1 (i,o1);
        always @(posedge clk)
                if (ce) o <= o1;
 
endmodule
 
// 5 slices / 10 LUTs / 7.702 ns
module cntlo8(
        input [7:0] i,
        output [3:0] o
);
 
        cntlz8 u1 (~i,o);
 
endmodule
 
 
module cntlo16(
        input [15:0] i,
        output [4:0] o
);
 
        cntlz16 u1 (~i,o);
 
endmodule
 
 
module cntlo32(
        input [31:0] i,
        output [5:0] o
);
 
        cntlz32 u1 (~i,o);
 
endmodule
 
 
module cntlo48(
        input [47:0] i,
        output [5:0] o
);
 
        cntlz48 u1 (~i,o);
 
endmodule
 
 
// 59 slices / 99 LUTs / 14.065 ns
module cntlo64(
        input [63:0] i,
        output [6:0] o
);
 
        cntlz64 u1 (~i,o);
 
endmodule
 
module cntlo80(
        input [79:0] i,
        output [6:0] o
);
 
        cntlz80 u1 (~i,o);
 
endmodule
 
module cntlo128(
        input [127:0] i,
        output [7:0] o
);
 
        cntlz128 u1 (~i,o);
 
endmodule
 

Browse

Tools

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog/] [lib/] [cntlz.sv] - Blame information for rev 63

Line No.	Rev	Author	Line
1	63	robfinch	`timescale 1ns / 1ps
2			`// ============================================================================`
3			`// __`
4			`// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo`
5			`// \ __ / All rights reserved.`
6			`// \/_// robfinch@finitron.ca`
7			`// \|\|`
8			`//`
9			`// cntlz.v`
10			`// - count number of leading zeros in a byte`
11			`// - count number of leading ones in a byte`
12			`// - simple fast approach - lookup table`
13			`//`
14			`// BSD 3-Clause License`
15			`// Redistribution and use in source and binary forms, with or without`
16			`// modification, are permitted provided that the following conditions are met:`
17			`//`
18			`// 1. Redistributions of source code must retain the above copyright notice, this`
19			`// list of conditions and the following disclaimer.`
20			`//`
21			`// 2. Redistributions in binary form must reproduce the above copyright notice,`
22			`// this list of conditions and the following disclaimer in the documentation`
23			`// and/or other materials provided with the distribution.`
24			`//`
25			`// 3. Neither the name of the copyright holder nor the names of its`
26			`// contributors may be used to endorse or promote products derived from`
27			`// this software without specific prior written permission.`
28			`//`
29			`// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
30			`// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE`
31			`// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
32			`// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE`
33			`// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
34			`// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR`
35			`// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER`
36			`// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,`
37			`// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE`
38			`// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
39			`//`
40			`// ============================================================================`
41
42			`module cntlz8(`
43			`input [7:0] i,`
44			`output reg [3:0] o`
45			`);`
46
47			`always_comb`
48			`case (i)`
49			`8'b00000000: o = 8;`
50			`8'b00000001: o = 7;`
51			`8'b00000010: o = 6;`
52			`8'b00000011: o = 6;`
53			`8'b00000100: o = 5;`
54			`8'b00000101: o = 5;`
55			`8'b00000110: o = 5;`
56			`8'b00000111: o = 5;`
57			`8'b00001000: o = 4;`
58			`8'b00001001: o = 4;`
59			`8'b00001010: o = 4;`
60			`8'b00001011: o = 4;`
61			`8'b00001100: o = 4;`
62			`8'b00001101: o = 4;`
63			`8'b00001110: o = 4;`
64			`8'b00001111: o = 4;`
65
66			`8'b00010000: o = 3;`
67			`8'b00010001: o = 3;`
68			`8'b00010010: o = 3;`
69			`8'b00010011: o = 3;`
70			`8'b00010100: o = 3;`
71			`8'b00010101: o = 3;`
72			`8'b00010110: o = 3;`
73			`8'b00010111: o = 3;`
74			`8'b00011000: o = 3;`
75			`8'b00011001: o = 3;`
76			`8'b00011010: o = 3;`
77			`8'b00011011: o = 3;`
78			`8'b00011100: o = 3;`
79			`8'b00011101: o = 3;`
80			`8'b00011110: o = 3;`
81			`8'b00011111: o = 3;`
82
83			`8'b00100000: o = 2;`
84			`8'b00100001: o = 2;`
85			`8'b00100010: o = 2;`
86			`8'b00100011: o = 2;`
87			`8'b00100100: o = 2;`
88			`8'b00100101: o = 2;`
89			`8'b00100110: o = 2;`
90			`8'b00100111: o = 2;`
91			`8'b00101000: o = 2;`
92			`8'b00101001: o = 2;`
93			`8'b00101010: o = 2;`
94			`8'b00101011: o = 2;`
95			`8'b00101100: o = 2;`
96			`8'b00101101: o = 2;`
97			`8'b00101110: o = 2;`
98			`8'b00101111: o = 2;`
99
100			`8'b00110000: o = 2;`
101			`8'b00110001: o = 2;`
102			`8'b00110010: o = 2;`
103			`8'b00110011: o = 2;`
104			`8'b00110100: o = 2;`
105			`8'b00110101: o = 2;`
106			`8'b00110110: o = 2;`
107			`8'b00110111: o = 2;`
108			`8'b00111000: o = 2;`
109			`8'b00111001: o = 2;`
110			`8'b00111010: o = 2;`
111			`8'b00111011: o = 2;`
112			`8'b00111100: o = 2;`
113			`8'b00111101: o = 2;`
114			`8'b00111110: o = 2;`
115			`8'b00111111: o = 2;`
116
117			`// 44 - 1`
118			`8'b01000000: o = 1;`
119			`8'b01000001: o = 1;`
120			`8'b01000010: o = 1;`
121			`8'b01000011: o = 1;`
122			`8'b01000100: o = 1;`
123			`8'b01000101: o = 1;`
124			`8'b01000110: o = 1;`
125			`8'b01000111: o = 1;`
126			`8'b01001000: o = 1;`
127			`8'b01001001: o = 1;`
128			`8'b01001010: o = 1;`
129			`8'b01001011: o = 1;`
130			`8'b01001100: o = 1;`
131			`8'b01001101: o = 1;`
132			`8'b01001110: o = 1;`
133			`8'b01001111: o = 1;`
134
135			`8'b01010000: o = 1;`
136			`8'b01010001: o = 1;`
137			`8'b01010010: o = 1;`
138			`8'b01010011: o = 1;`
139			`8'b01010100: o = 1;`
140			`8'b01010101: o = 1;`
141			`8'b01010110: o = 1;`
142			`8'b01010111: o = 1;`
143			`8'b01011000: o = 1;`
144			`8'b01011001: o = 1;`
145			`8'b01011010: o = 1;`
146			`8'b01011011: o = 1;`
147			`8'b01011100: o = 1;`
148			`8'b01011101: o = 1;`
149			`8'b01011110: o = 1;`
150			`8'b01011111: o = 1;`
151
152			`8'b01100000: o = 1;`
153			`8'b01100001: o = 1;`
154			`8'b01100010: o = 1;`
155			`8'b01100011: o = 1;`
156			`8'b01100100: o = 1;`
157			`8'b01100101: o = 1;`
158			`8'b01100110: o = 1;`
159			`8'b01100111: o = 1;`
160			`8'b01101000: o = 1;`
161			`8'b01101001: o = 1;`
162			`8'b01101010: o = 1;`
163			`8'b01101011: o = 1;`
164			`8'b01101100: o = 1;`
165			`8'b01101101: o = 1;`
166			`8'b01101110: o = 1;`
167			`8'b01101111: o = 1;`
168
169			`8'b01110000: o = 1;`
170			`8'b01110001: o = 1;`
171			`8'b01110010: o = 1;`
172			`8'b01110011: o = 1;`
173			`8'b01110100: o = 1;`
174			`8'b01110101: o = 1;`
175			`8'b01110110: o = 1;`
176			`8'b01110111: o = 1;`
177			`8'b01111000: o = 1;`
178			`8'b01111001: o = 1;`
179			`8'b01111010: o = 1;`
180			`8'b01111011: o = 1;`
181			`8'b01111100: o = 1;`
182			`8'b01111101: o = 1;`
183			`8'b01111110: o = 1;`
184			`8'b01111111: o = 1;`
185
186			`// - 2`
187			`8'b10000000: o = 0;`
188			`8'b10000001: o = 0;`
189			`8'b10000010: o = 0;`
190			`8'b10000011: o = 0;`
191			`8'b10000100: o = 0;`
192			`8'b10000101: o = 0;`
193			`8'b10000110: o = 0;`
194			`8'b10000111: o = 0;`
195			`8'b10001000: o = 0;`
196			`8'b10001001: o = 0;`
197			`8'b10001010: o = 0;`
198			`8'b10001011: o = 0;`
199			`8'b10001100: o = 0;`
200			`8'b10001101: o = 0;`
201			`8'b10001110: o = 0;`
202			`8'b10001111: o = 0;`
203
204			`8'b10010000: o = 0;`
205			`8'b10010001: o = 0;`
206			`8'b10010010: o = 0;`
207			`8'b10010011: o = 0;`
208			`8'b10010100: o = 0;`
209			`8'b10010101: o = 0;`
210			`8'b10010110: o = 0;`
211			`8'b10010111: o = 0;`
212			`8'b10011000: o = 0;`
213			`8'b10011001: o = 0;`
214			`8'b10011010: o = 0;`
215			`8'b10011011: o = 0;`
216			`8'b10011100: o = 0;`
217			`8'b10011101: o = 0;`
218			`8'b10011110: o = 0;`
219			`8'b10011111: o = 0;`
220
221			`8'b10100000: o = 0;`
222			`8'b10100001: o = 0;`
223			`8'b10100010: o = 0;`
224			`8'b10100011: o = 0;`
225			`8'b10100100: o = 0;`
226			`8'b10100101: o = 0;`
227			`8'b10100110: o = 0;`
228			`8'b10100111: o = 0;`
229			`8'b10101000: o = 0;`
230			`8'b10101001: o = 0;`
231			`8'b10101010: o = 0;`
232			`8'b10101011: o = 0;`
233			`8'b10101100: o = 0;`
234			`8'b10101101: o = 0;`
235			`8'b10101110: o = 0;`
236			`8'b10101111: o = 0;`
237
238			`8'b10110000: o = 0;`
239			`8'b10110001: o = 0;`
240			`8'b10110010: o = 0;`
241			`8'b10110011: o = 0;`
242			`8'b10110100: o = 0;`
243			`8'b10110101: o = 0;`
244			`8'b10110110: o = 0;`
245			`8'b10110111: o = 0;`
246			`8'b10111000: o = 0;`
247			`8'b10111001: o = 0;`
248			`8'b10111010: o = 0;`
249			`8'b10111011: o = 0;`
250			`8'b10111100: o = 0;`
251			`8'b10111101: o = 0;`
252			`8'b10111110: o = 0;`
253			`8'b10111111: o = 0;`
254
255			`// 44 - 3`
256			`8'b11000000: o = 0;`
257			`8'b11000001: o = 0;`
258			`8'b11000010: o = 0;`
259			`8'b11000011: o = 0;`
260			`8'b11000100: o = 0;`
261			`8'b11000101: o = 0;`
262			`8'b11000110: o = 0;`
263			`8'b11000111: o = 0;`
264			`8'b11001000: o = 0;`
265			`8'b11001001: o = 0;`
266			`8'b11001010: o = 0;`
267			`8'b11001011: o = 0;`
268			`8'b11001100: o = 0;`
269			`8'b11001101: o = 0;`
270			`8'b11001110: o = 0;`
271			`8'b11001111: o = 0;`
272
273			`8'b11010000: o = 0;`
274			`8'b11010001: o = 0;`
275			`8'b11010010: o = 0;`
276			`8'b11010011: o = 0;`
277			`8'b11010100: o = 0;`
278			`8'b11010101: o = 0;`
279			`8'b11010110: o = 0;`
280			`8'b11010111: o = 0;`
281			`8'b11011000: o = 0;`
282			`8'b11011001: o = 0;`
283			`8'b11011010: o = 0;`
284			`8'b11011011: o = 0;`
285			`8'b11011100: o = 0;`
286			`8'b11011101: o = 0;`
287			`8'b11011110: o = 0;`
288			`8'b11011111: o = 0;`
289
290			`8'b11100000: o = 0;`
291			`8'b11100001: o = 0;`
292			`8'b11100010: o = 0;`
293			`8'b11100011: o = 0;`
294			`8'b11100100: o = 0;`
295			`8'b11100101: o = 0;`
296			`8'b11100110: o = 0;`
297			`8'b11100111: o = 0;`
298			`8'b11101000: o = 0;`
299			`8'b11101001: o = 0;`
300			`8'b11101010: o = 0;`
301			`8'b11101011: o = 0;`
302			`8'b11101100: o = 0;`
303			`8'b11101101: o = 0;`
304			`8'b11101110: o = 0;`
305			`8'b11101111: o = 0;`
306
307			`8'b11110000: o = 0;`
308			`8'b11110001: o = 0;`
309			`8'b11110010: o = 0;`
310			`8'b11110011: o = 0;`
311			`8'b11110100: o = 0;`
312			`8'b11110101: o = 0;`
313			`8'b11110110: o = 0;`
314			`8'b11110111: o = 0;`
315			`8'b11111000: o = 0;`
316			`8'b11111001: o = 0;`
317			`8'b11111010: o = 0;`
318			`8'b11111011: o = 0;`
319			`8'b11111100: o = 0;`
320			`8'b11111101: o = 0;`
321			`8'b11111110: o = 0;`
322			`8'b11111111: o = 0;`
323
324			`endcase`
325
326
327			`endmodule`
328
329
330			`module cntlz16(`
331			`input [15:0] i,`
332			`output [4:0] o`
333			`);`
334
335			`wire [3:0] cnt1, cnt2;`
336
337			`cntlz8 u1 (i[ 7:0],cnt1);`
338			`cntlz8 u2 (i[15:8],cnt2);`
339
340			`assign o = cnt2[3] ? cnt1 + 4'h8 : cnt2;`
341
342			`endmodule`
343
344
345			`// 39 slices / 67 LUTs / 19.3ns`
346			`module cntlz24(`
347			`input [23:0] i,`
348			`output [4:0] o`
349			`);`
350
351			`wire [3:0] cnt1, cnt2, cnt3;`
352
353			`// cntlz8 results in faster result than cntlz16`
354			`cntlz8 u1 (i[ 7: 0],cnt1);`
355			`cntlz8 u2 (i[15: 8],cnt2);`
356			`cntlz8 u3 (i[23:16],cnt3);`
357
358			`assign o =`
359			`!cnt3[3] ? cnt3 :`
360			`!cnt2[3] ? cnt2 + 5'd8 :`
361			`cnt1 + 5'd16;`
362
363			`endmodule`
364
365			`// 39 slices / 67 LUTs / 19.3ns`
366			`module cntlz32(`
367			`input [31:0] i,`
368			`output [5:0] o`
369			`);`
370
371			`wire [3:0] cnt1, cnt2, cnt3, cnt4;`
372
373			`// cntlz8 results in faster result than cntlz16`
374			`cntlz8 u1 (i[ 7: 0],cnt1);`
375			`cntlz8 u2 (i[15: 8],cnt2);`
376			`cntlz8 u3 (i[23:16],cnt3);`
377			`cntlz8 u4 (i[31:24],cnt4);`
378
379			`assign o =`
380			`!cnt4[3] ? cnt4 :`
381			`!cnt3[3] ? cnt3 + 6'd8 :`
382			`!cnt2[3] ? cnt2 + 6'd16 :`
383			`cnt1 + 6'd24;`
384
385			`endmodule`
386
387
388			`// 88 slices / 154 LUTs / 22.5 ns`
389			`module cntlz48(`
390			`input [47:0] i,`
391			`output [5:0] o`
392			`);`
393
394			`wire [4:0] cnt1, cnt2, cnt3;`
395
396			`cntlz16 u1 (i[15: 0],cnt1);`
397			`cntlz16 u2 (i[31:16],cnt2);`
398			`cntlz16 u3 (i[47:32],cnt3);`
399
400			`assign o =`
401			`!cnt3[4] ? cnt3 :`
402			`!cnt2[4] ? cnt2 + 7'd16 :`
403			`cnt1 + 7'd32;`
404
405			`endmodule`
406
407
408			`// 88 slices / 154 LUTs / 22.5 ns`
409			`module cntlz64(`
410			`input [63:0] i,`
411			`output [6:0] o`
412			`);`
413
414			`wire [4:0] cnt1, cnt2, cnt3, cnt4;`
415
416			`cntlz16 u1 (i[15: 0],cnt1);`
417			`cntlz16 u2 (i[31:16],cnt2);`
418			`cntlz16 u3 (i[47:32],cnt3);`
419			`cntlz16 u4 (i[63:48],cnt4);`
420
421			`assign o =`
422			`!cnt4[4] ? cnt4 :`
423			`!cnt3[4] ? cnt3 + 7'd16 :`
424			`!cnt2[4] ? cnt2 + 7'd32 :`
425			`cnt1 + 7'd48;`
426
427			`endmodule`
428
429
430			`module cntlz80(`
431			`input [79:0] i,`
432			`output [6:0] o`
433			`);`
434
435			`wire [4:0] cnt3;`
436			`wire [5:0] cnt1, cnt2;`
437
438			`cntlz32 u1 (i[31: 0],cnt1);`
439			`cntlz32 u2 (i[63:32],cnt2);`
440			`cntlz16 u3 (i[79:64],cnt3);`
441
442			`assign o =`
443			`!cnt3[4] ? {2'b0,cnt3} :`
444			`!cnt2[5] ? {1'b0,cnt2} + 8'd16 :`
445			`{1'b0,cnt1} + 7'd48;`
446
447			`endmodule`
448
449
450			`module cntlz96(`
451			`input [95:0] i,`
452			`output [7:0] o`
453			`);`
454
455			`wire [5:0] cnt1, cnt2, cnt3;`
456
457			`cntlz32 u1 (i[31: 0],cnt1);`
458			`cntlz32 u2 (i[63:32],cnt2);`
459			`cntlz32 u3 (i[95:64],cnt3);`
460
461			`assign o =`
462			`!cnt3[5] ? cnt3 :`
463			`!cnt2[5] ? cnt2 + 8'd32 :`
464			`cnt1 + 8'd64;`
465
466			`endmodule`
467
468
469			`module cntlz128(`
470			`input [127:0] i,`
471			`output [7:0] o`
472			`);`
473
474			`wire [5:0] cnt1, cnt2, cnt3, cnt4;`
475
476			`cntlz32 u1 (i[31: 0],cnt1);`
477			`cntlz32 u2 (i[63:32],cnt2);`
478			`cntlz32 u3 (i[95:64],cnt3);`
479			`cntlz32 u4 (i[127:96],cnt4);`
480
481			`assign o =`
482			`!cnt4[5] ? cnt4 :`
483			`!cnt3[5] ? cnt3 + 8'd32 :`
484			`!cnt2[5] ? cnt2 + 8'd64 :`
485			`cnt1 + 8'd96;`
486
487			`endmodule`
488
489
490			`module cntlz192(`
491			`input [191:0] i,`
492			`output [7:0] o`
493			`);`
494
495			`wire [5:0] cnt1, cnt2, cnt3, cnt4, cnt5, cnt6;`
496
497			`cntlz32 u1 (i[31: 0],cnt1);`
498			`cntlz32 u2 (i[63:32],cnt2);`
499			`cntlz32 u3 (i[95:64],cnt3);`
500			`cntlz32 u4 (i[127:96],cnt4);`
501			`cntlz32 u5 (i[159:128],cnt5);`
502			`cntlz32 u6 (i[191:160],cnt6);`
503
504			`assign o =`
505			`!cnt6[5] ? cnt6 :`
506			`!cnt5[5] ? cnt5 + 8'd32 :`
507			`!cnt4[5] ? cnt4 + 8'd64:`
508			`!cnt3[5] ? cnt3 + 8'd96 :`
509			`!cnt2[5] ? cnt2 + 8'd128 :`
510			`cnt1 + 8'd160;`
511
512			`endmodule`
513
514
515			`module cntlz32Reg(`
516			`input clk,`
517			`input ce,`
518			`input [31:0] i,`
519			`output reg [5:0] o`
520			`);`
521
522			`wire [5:0] o1;`
523			`cntlz32 u1 (i,o1);`
524			`always @(posedge clk)`
525			`if (ce) o <= o1;`
526
527			`endmodule`
528
529
530			`module cntlz64Reg(`
531			`input clk,`
532			`input ce,`
533			`input [63:0] i,`
534			`output reg [6:0] o`
535			`);`
536
537			`wire [6:0] o1;`
538			`cntlz64 u1 (i,o1);`
539			`always @(posedge clk)`
540			`if (ce) o <= o1;`
541
542			`endmodule`
543
544			`module cntlz80Reg(`
545			`input clk,`
546			`input ce,`
547			`input [79:0] i,`
548			`output reg [6:0] o`
549			`);`
550
551			`wire [6:0] o1;`
552			`cntlz80 u1 (i,o1);`
553			`always @(posedge clk)`
554			`if (ce) o <= o1;`
555
556			`endmodule`
557
558			`module cntlz96Reg(`
559			`input clk,`
560			`input ce,`
561			`input [95:0] i,`
562			`output reg [7:0] o`
563			`);`
564
565			`wire [7:0] o1;`
566			`cntlz96 u1 (i,o1);`
567			`always @(posedge clk)`
568			`if (ce) o <= o1;`
569
570			`endmodule`
571
572			`module cntlz128Reg(`
573			`input clk,`
574			`input ce,`
575			`input [127:0] i,`
576			`output reg [7:0] o`
577			`);`
578
579			`wire [7:0] o1;`
580			`cntlz128 u1 (i,o1);`
581			`always @(posedge clk)`
582			`if (ce) o <= o1;`
583
584			`endmodule`
585
586			`module cntlz192Reg(`
587			`input clk,`
588			`input ce,`
589			`input [191:0] i,`
590			`output reg [7:0] o`
591			`);`
592
593			`wire [7:0] o1;`
594			`cntlz192 u1 (i,o1);`
595			`always @(posedge clk)`
596			`if (ce) o <= o1;`
597
598			`endmodule`
599
600			`// 5 slices / 10 LUTs / 7.702 ns`
601			`module cntlo8(`
602			`input [7:0] i,`
603			`output [3:0] o`
604			`);`
605
606			`cntlz8 u1 (~i,o);`
607
608			`endmodule`
609
610
611			`module cntlo16(`
612			`input [15:0] i,`
613			`output [4:0] o`
614			`);`
615
616			`cntlz16 u1 (~i,o);`
617
618			`endmodule`
619
620
621			`module cntlo32(`
622			`input [31:0] i,`
623			`output [5:0] o`
624			`);`
625
626			`cntlz32 u1 (~i,o);`
627
628			`endmodule`
629
630
631			`module cntlo48(`
632			`input [47:0] i,`
633			`output [5:0] o`
634			`);`
635
636			`cntlz48 u1 (~i,o);`
637
638			`endmodule`
639
640
641			`// 59 slices / 99 LUTs / 14.065 ns`
642			`module cntlo64(`
643			`input [63:0] i,`
644			`output [6:0] o`
645			`);`
646
647			`cntlz64 u1 (~i,o);`
648
649			`endmodule`
650
651			`module cntlo80(`
652			`input [79:0] i,`
653			`output [6:0] o`
654			`);`
655
656			`cntlz80 u1 (~i,o);`
657
658			`endmodule`
659
660			`module cntlo128(`
661			`input [127:0] i,`
662			`output [7:0] o`
663			`);`
664
665			`cntlz128 u1 (~i,o);`
666
667			`endmodule`
668