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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [lib/] [delay.v] - Blame information for rev 6

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/* ===============================================================
        (C) 2006  Robert Finch
        All rights reserved.
        rob@birdcomputer.ca
 
        delay.v
                - delays signals by so many clock cycles
 
 
        This source code is free for use and modification for
        non-commercial or evaluation purposes, provided this
        copyright statement and disclaimer remains present in
        the file.
 
        If you do modify the code, please state the origin and
        note that you have modified the code.
 
        NO WARRANTY.
        THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF
        ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume
        the entire risk of using the Work.
 
        IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
        ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES
        WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR
        RELATIONSHIP WITH THE AUTHOR.
 
        IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU
        TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE
        WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED
        TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS
        OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK,
        AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS
        FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED
        USE.
 
=============================================================== */
 
module delay1
        #(parameter WID = 1)
        (
        input clk,
        input ce,
        input [WID:1] i,
        output reg [WID:1] o
        );
 
        always @(posedge clk)
                if (ce)
                        o <= i;
 
endmodule
 
 
module delay2
        #(parameter WID = 1)
        (
        input clk,
        input ce,
        input [WID:1] i,
        output reg [WID:1] o
        );
 
 
        reg     [WID:1] r1;
 
        always @(posedge clk)
                if (ce)
                        r1 <= i;
 
        always @(posedge clk)
                if (ce)
                        o <= r1;
 
endmodule
 
 
module delay3
        #(parameter WID = 1)
        (
        input clk,
        input ce,
        input [WID:1] i,
        output reg [WID:1] o
        );
 
        reg     [WID:1] r1, r2;
 
        always @(posedge clk)
                if (ce)
                        r1 <= i;
 
        always @(posedge clk)
                if (ce)
                        r2 <= r1;
 
        always @(posedge clk)
                if (ce)
                        o <= r2;
 
endmodule
 
module delay4
        #(parameter WID = 1)
        (
        input clk,
        input ce,
        input [WID:1] i,
        output reg [WID:1] o
        );
 
        reg     [WID:1] r1, r2, r3;
 
        always @(posedge clk)
                if (ce)
                        r1 <= i;
 
        always @(posedge clk)
                if (ce)
                        r2 <= r1;
 
        always @(posedge clk)
                if (ce)
                        r3 <= r2;
 
        always @(posedge clk)
                if (ce)
                        o <= r3;
 
endmodule
 
 
module delay5
#(parameter WID = 1)
(
        input clk,
        input ce,
        input [WID:1] i,
        output reg [WID:1] o
);
 
        reg     [WID:1] r1, r2, r3, r4;
 
        always @(posedge clk)
                if (ce) r1 <= i;
 
        always @(posedge clk)
                if (ce) r2 <= r1;
 
        always @(posedge clk)
                if (ce) r3 <= r2;
 
        always @(posedge clk)
                if (ce) r4 <= r3;
 
        always @(posedge clk)
                if (ce) o <= r4;
 
endmodule
 

Line No.	Rev	Author	Line
1	5	robfinch	`/* ===============================================================`
2			`(C) 2006 Robert Finch`
3			`All rights reserved.`
4			`rob@birdcomputer.ca`
5
6			`delay.v`
7			`- delays signals by so many clock cycles`
8
9
10			`This source code is free for use and modification for`
11			`non-commercial or evaluation purposes, provided this`
12			`copyright statement and disclaimer remains present in`
13			`the file.`
14
15			`If you do modify the code, please state the origin and`
16			`note that you have modified the code.`
17
18			`NO WARRANTY.`
19			`THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF`
20			`ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume`
21			`the entire risk of using the Work.`
22
23			`IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR`
24			`ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES`
25			`WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR`
26			`RELATIONSHIP WITH THE AUTHOR.`
27
28			`IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU`
29			`TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE`
30			`WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED`
31			`TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS`
32			`OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK,`
33			`AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS`
34			`FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED`
35			`USE.`
36
37			`=============================================================== */`
38
39			`module delay1`
40			`#(parameter WID = 1)`
41			`(`
42			`input clk,`
43			`input ce,`
44			`input [WID:1] i,`
45			`output reg [WID:1] o`
46			`);`
47
48			`always @(posedge clk)`
49			`if (ce)`
50			`o <= i;`
51
52			`endmodule`
53
54
55			`module delay2`
56			`#(parameter WID = 1)`
57			`(`
58			`input clk,`
59			`input ce,`
60			`input [WID:1] i,`
61			`output reg [WID:1] o`
62			`);`
63
64
65			`reg [WID:1] r1;`
66
67			`always @(posedge clk)`
68			`if (ce)`
69			`r1 <= i;`
70
71			`always @(posedge clk)`
72			`if (ce)`
73			`o <= r1;`
74
75			`endmodule`
76
77
78			`module delay3`
79			`#(parameter WID = 1)`
80			`(`
81			`input clk,`
82			`input ce,`
83			`input [WID:1] i,`
84			`output reg [WID:1] o`
85			`);`
86
87			`reg [WID:1] r1, r2;`
88
89			`always @(posedge clk)`
90			`if (ce)`
91			`r1 <= i;`
92
93			`always @(posedge clk)`
94			`if (ce)`
95			`r2 <= r1;`
96
97			`always @(posedge clk)`
98			`if (ce)`
99			`o <= r2;`
100
101			`endmodule`
102
103			`module delay4`
104			`#(parameter WID = 1)`
105			`(`
106			`input clk,`
107			`input ce,`
108			`input [WID:1] i,`
109			`output reg [WID:1] o`
110			`);`
111
112			`reg [WID:1] r1, r2, r3;`
113
114			`always @(posedge clk)`
115			`if (ce)`
116			`r1 <= i;`
117
118			`always @(posedge clk)`
119			`if (ce)`
120			`r2 <= r1;`
121
122			`always @(posedge clk)`
123			`if (ce)`
124			`r3 <= r2;`
125
126			`always @(posedge clk)`
127			`if (ce)`
128			`o <= r3;`
129
130			`endmodule`
131
132
133			`module delay5`
134			`#(parameter WID = 1)`
135			`(`
136			`input clk,`
137			`input ce,`
138			`input [WID:1] i,`
139			`output reg [WID:1] o`
140			`);`
141
142			`reg [WID:1] r1, r2, r3, r4;`
143
144			`always @(posedge clk)`
145			`if (ce) r1 <= i;`
146
147			`always @(posedge clk)`
148			`if (ce) r2 <= r1;`
149
150			`always @(posedge clk)`
151			`if (ce) r3 <= r2;`
152
153			`always @(posedge clk)`
154			`if (ce) r4 <= r3;`
155
156			`always @(posedge clk)`
157			`if (ce) o <= r4;`
158
159			`endmodule`
160

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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [lib/] [delay.v] - Blame information for rev 6