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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [lib/] [delay.v] - Blame information for rev 6

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1 5 robfinch
/* ===============================================================
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        (C) 2006  Robert Finch
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        All rights reserved.
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        rob@birdcomputer.ca
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        delay.v
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                - delays signals by so many clock cycles
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        This source code is free for use and modification for
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        non-commercial or evaluation purposes, provided this
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        copyright statement and disclaimer remains present in
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        the file.
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        If you do modify the code, please state the origin and
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        note that you have modified the code.
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        NO WARRANTY.
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        THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF
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        ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume
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        the entire risk of using the Work.
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        IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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        ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES
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        WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR
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        RELATIONSHIP WITH THE AUTHOR.
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        IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU
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        TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE
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        WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED
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        TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS
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        OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK,
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        AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS
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        FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED
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        USE.
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=============================================================== */
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module delay1
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        #(parameter WID = 1)
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        (
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        input clk,
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        input ce,
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        input [WID:1] i,
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        output reg [WID:1] o
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        );
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        always @(posedge clk)
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                if (ce)
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                        o <= i;
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endmodule
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module delay2
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        #(parameter WID = 1)
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        (
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        input clk,
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        input ce,
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        input [WID:1] i,
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        output reg [WID:1] o
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        );
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        reg     [WID:1] r1;
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        always @(posedge clk)
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                if (ce)
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                        r1 <= i;
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        always @(posedge clk)
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                if (ce)
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                        o <= r1;
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endmodule
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module delay3
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        #(parameter WID = 1)
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        (
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        input clk,
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        input ce,
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        input [WID:1] i,
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        output reg [WID:1] o
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        );
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        reg     [WID:1] r1, r2;
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        always @(posedge clk)
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                if (ce)
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                        r1 <= i;
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        always @(posedge clk)
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                if (ce)
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                        r2 <= r1;
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        always @(posedge clk)
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                if (ce)
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                        o <= r2;
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endmodule
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module delay4
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        #(parameter WID = 1)
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        (
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        input clk,
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        input ce,
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        input [WID:1] i,
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        output reg [WID:1] o
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        );
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        reg     [WID:1] r1, r2, r3;
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        always @(posedge clk)
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                if (ce)
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                        r1 <= i;
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        always @(posedge clk)
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                if (ce)
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                        r2 <= r1;
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        always @(posedge clk)
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                if (ce)
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                        r3 <= r2;
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        always @(posedge clk)
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                if (ce)
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                        o <= r3;
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endmodule
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module delay5
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#(parameter WID = 1)
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(
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        input clk,
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        input ce,
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        input [WID:1] i,
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        output reg [WID:1] o
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);
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        reg     [WID:1] r1, r2, r3, r4;
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        always @(posedge clk)
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                if (ce) r1 <= i;
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        always @(posedge clk)
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                if (ce) r2 <= r1;
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        always @(posedge clk)
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                if (ce) r3 <= r2;
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        always @(posedge clk)
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                if (ce) r4 <= r3;
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        always @(posedge clk)
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                if (ce) o <= r4;
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endmodule
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