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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [lib/] [vtdl.v] - Blame information for rev 61

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1 61 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2007-2021  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      vtdl - variable tap delay line
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//              (dynamic shift register)
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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//    Notes:
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//
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//      This module acts like a clocked delay line with a variable tap.
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//      Miscellaneous usage in rate control circuitry such as fifo's.
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//      Capable of delaying a signal bus.
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//      Signal bus width is specified with the WID parameter.
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//
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//      Verilog 1995
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// =============================================================================
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//
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module vtdl(clk, ce, a, d, q);
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parameter WID = 8;
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parameter DEP = 16;
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localparam AMSB = DEP>64?6:DEP>32?5:DEP>16?4:DEP>8?3:DEP>4?2:DEP>2?1:0;
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input clk;
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input ce;
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input [AMSB:0] a;
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input [WID-1:0] d;
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output [WID-1:0] q;
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reg [WID-1:0] m [DEP-1:0];
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integer n;
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always @(posedge clk)
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        if (ce) begin
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                for (n = 1; n < DEP; n = n + 1)
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                        m[n] <= m[n-1];
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                m[0] <= d;
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        end
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assign q = m[a];
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endmodule
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module vtdlx1(clk, ce, a, d, q);
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parameter DEP = 16;
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localparam AMSB = DEP>64?6:DEP>32?5:DEP>16?4:DEP>8?3:DEP>4?2:DEP>2?1:0;
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input clk;
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input ce;
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input [AMSB:0] a;
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input d;
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output q;
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reg [DEP-1:0] m;
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integer n;
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always @(posedge clk)
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        if (ce) begin
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                for (n = 1; n < DEP; n = n + 1)
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                        m[n] <= m[n-1];
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                m[0] <= d;
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        end
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assign q = m[a];
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endmodule

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