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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [BCDAdd8NClk.sv] - Blame information for rev 84

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1 66 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2012-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      BCDAdd8NClk.sv
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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// The following added breaks up the carry chain.
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//
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// The adder is organized into three rows and N*2 columns of digits. The first
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// row is set to the input a, b operands. The carry for the first row and column
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// is set to the carry input. The operands in a row are added without taking
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// carry into consideration. But the carry out is recorded and added as the 'B'
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// operand in the next row. The sum from one row is fed as the 'A' operand into
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// the next row. Values (sum and carry) are moved between rows in a clocked
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// fashion. The first row contains full BCD adders. After that only a single
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// bit is added.
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//
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// There cannot be more than three rows required. The worst case scenario occurs
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// when all the inputs are at a max and there is a carry input. This generates a
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// carry output from each digit in the second row.
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//
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// In that case
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//   99999999
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// + 99999999
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// +        1 (carry in)
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//---------------
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//  188888889           <- first row result
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// + 11111110           <- carries out of first row
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//---------------
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//  199999999   <- second row result
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64 70 robfinch
module BCDAdd8NClk(clk, a, b, o, ci, co);
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parameter N=33;
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input clk;
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input [N*8-1:0] a;
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input [N*8-1:0] b;
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output reg [N*8-1:0] o;
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input ci;
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output reg co;
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reg [N-1:0] c [0:2];
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wire [N*8-1:0] o1 [0:2];
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reg [N*8-1:0] o2 [0:2];
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wire [N-1:0] d [0:2];
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genvar g,k;
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generate begin : gBCDadd
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for (k = 0; k < 3; k = k + 1) begin
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        for (g = 0; g < N; g = g + 1) begin
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                initial begin
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                        c[k][g] <= 'b0;
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                end
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                BCDAdd u1 (
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                        .ci(k==0 && g==0 ? ci : 1'b0),
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                        .a(k==0 ? a[g*8+7:g*8] : o2[k-1][g*8+7:g*8]),
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                        .b(k==0 ? b[g*8+7:g*8] : {7'h00,c[k-1][g]}),
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                        .o(o1[k][g*8+7:g*8]),
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                        .c(d[k][g])
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                );
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                always_ff @(posedge clk)
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                        o2[k] <= o1[k];
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                always_ff @(posedge clk)
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                        c[k][g] <= d[k][g];
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        end
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end
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always_ff @(posedge clk)
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begin
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        o <= o1[2];
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        co <= c[2][N-1]|c[1][N-1]|c[0][N-1];
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end
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end
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endgenerate
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endmodule

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