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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [BCDMath.sv] - Blame information for rev 80

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1 66 robfinch 
`timescale 1ns / 1ps
2 
// ============================================================================
3 
//        __
4 
//   \\__/ o\    (C) 2012-2022  Robert Finch, Waterloo
5 
//    \  __ /    All rights reserved.
6 
//     \/_//     robfinch@finitron.ca
7 
//       ||
8 
//
9 
//      BCDMath.sv
10 
//
11 
// BSD 3-Clause License
12 
// Redistribution and use in source and binary forms, with or without
13 
// modification, are permitted provided that the following conditions are met:
14 
//
15 
// 1. Redistributions of source code must retain the above copyright notice, this
16 
//    list of conditions and the following disclaimer.
17 
//
18 
// 2. Redistributions in binary form must reproduce the above copyright notice,
19 
//    this list of conditions and the following disclaimer in the documentation
20 
//    and/or other materials provided with the distribution.
21 
//
22 
// 3. Neither the name of the copyright holder nor the names of its
23 
//    contributors may be used to endorse or promote products derived from
24 
//    this software without specific prior written permission.
25 
//
26 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29 
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
30 
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32 
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
33 
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 
//
37 
// ============================================================================
38 
//
39 
// Could use the following approach for add/sub but it ends up being larger
40 
// than using an adjustment lookup table.
41 
 
42 
module BCDAddNyb(ci,a,b,o,c);
43 
input ci;               // carry input
44 
input [3:0] a;
45 
input [3:0] b;
46 
output [3:0] o;
47 
output c;
48 
 
49 
wire c0;
50 
 
51 
reg [4:0] hsN0;
52 
always  @*
53 
begin
54 
        hsN0 = a[3:0] + b[3:0] + ci;
55 
        if (hsN0 > 5'd9)
56 
                hsN0 = hsN0 + 3'd6;
57 
end
58 
assign o = hsN0[3:0];
59 
assign c = hsN0[4];
60 
 
61 
endmodule
62 
 
63 
module BCDAdd(ci,a,b,o,c);
64 
input ci;               // carry input
65 
input [7:0] a;
66 
input [7:0] b;
67 
output [7:0] o;
68 
output c;
69 
 
70 
wire c0,c1;
71 
 
72 
wire [4:0] hsN0 = a[3:0] + b[3:0] + ci;
73 
wire [4:0] hsN1 = a[7:4] + b[7:4] + c0;
74 
 
75 
BCDAddAdjust u1 (hsN0,o[3:0],c0);
76 
BCDAddAdjust u2 (hsN1,o[7:4],c);
77 
 
78 
endmodule
79 
 
80 
module BCDAdd4(ci,a,b,o,c,c8);
81 
input ci;               // carry input
82 
input [15:0] a;
83 
input [15:0] b;
84 
output [15:0] o;
85 
output c;
86 
output c8;
87 
 
88 
wire c0,c1,c2;
89 
assign c8 = c1;
90 
 
91 
wire [4:0] hsN0 = a[3:0] + b[3:0] + ci;
92 
wire [4:0] hsN1 = a[7:4] + b[7:4] + c0;
93 
wire [4:0] hsN2 = a[11:8] + b[11:8] + c1;
94 
wire [4:0] hsN3 = a[15:12] + b[15:12] + c2;
95 
 
96 
BCDAddAdjust u1 (hsN0,o[3:0],c0);
97 
BCDAddAdjust u2 (hsN1,o[7:4],c1);
98 
BCDAddAdjust u3 (hsN2,o[11:8],c2);
99 
BCDAddAdjust u4 (hsN3,o[15:12],c);
100 
 
101 
endmodule
102 
 
103 80 robfinch 
module BCDAddNClk(clk,ci,a,b,o,co);
104 
parameter N=25;
105 
input clk;
106 
input ci;
107 66 robfinch 
input [N*4-1:0] a;
108 
input [N*4-1:0] b;
109 80 robfinch 
output reg [N*4-1:0] o;
110 
output reg co;
111 66 robfinch 
 
112 80 robfinch 
reg [N-1:0] cg;
113 
wire [N*4-1:0] s;
114 
reg [N*4-1:0] on [0:3];
115 
reg [3:0] cn;
116 
 
117 66 robfinch 
genvar g;
118 80 robfinch 
generate begin :gAdd
119 
        for (g = 0; g < N; g = g + 1)
120 
        BCDAddNyb u1 (
121 
                .ci(g==0 ? ci : cg[g-1]),
122 
                .a(a[g*4+3:g*4]),
123 
                .b(b[g*4+3:g*4]),
124 
                .o(s[g*4+3:g*4]),
125 
                .c(cg[g])
126 
        );
127 66 robfinch 
end
128 
endgenerate
129 
 
130 80 robfinch 
always_ff @(posedge clk)
131 
        on[0] <= s;
132 
always_ff @(posedge clk)
133 
        on[1] <= on[0];
134 
always_ff @(posedge clk)
135 
        on[2] <= on[1];
136 
always_ff @(posedge clk)
137 
        o <= on[2];
138 
always_ff @(posedge clk)
139 
        cn[0] <= cg[N-1];
140 
always_ff @(posedge clk)
141 
        cn[1] <= cn[0];
142 
always_ff @(posedge clk)
143 
        cn[2] <= cn[1];
144 
always_ff @(posedge clk)
145 
        co <= cn[2];
146 66 robfinch 
 
147 
endmodule
148 
 
149 80 robfinch 
module BCDAddN(ci,a,b,o,co);
150 
parameter N=25;
151 
input ci;
152 
input [N*4-1:0] a;
153 
input [N*4-1:0] b;
154 
output [N*4-1:0] o;
155 
output co;
156 66 robfinch 
 
157 80 robfinch 
reg [N-1:0] cg;
158 
wire [N*4-1:0] s;
159 66 robfinch 
 
160 80 robfinch 
genvar g;
161 
generate begin :gAdd
162 
        for (g = 0; g < N; g = g + 1)
163 
        BCDAddNyb u1 (
164 
                .ci(g==0 ? ci : cg[g-1]),
165 
                .a(a[g*4+3:g*4]),
166 
                .b(b[g*4+3:g*4]),
167 
                .o(s[g*4+3:g*4]),
168 
                .c(cg[g])
169 
        );
170 
end
171 
endgenerate
172 66 robfinch 
 
173 80 robfinch 
assign o = s;
174 
assign co = cg[N-1];
175 66 robfinch 
 
176 
endmodule
177 
 
178 80 robfinch 
/*
179 
module BCDAddN(ci,a,b,o,co);
180 66 robfinch 
parameter N=24;
181 
input ci;               // carry input
182 
input [N*4-1:0] a;
183 
input [N*4-1:0] b;
184 
output [N*4-1:0] o;
185 
output co;
186 
 
187 
genvar g;
188 80 robfinch 
generate begin : gBCDAddN
189 
reg [4:0] hsN [0:N-1];
190 66 robfinch 
wire [N:0] c;
191 
 
192 
assign c[0] = ci;
193 
assign co = c[N];
194 
 
195 
for (g = 0; g < N; g = g + 1)
196 
        always @*
197 80 robfinch 
                hsN[g] = a[g*4+3:g*4] + b[g*4+3:g*4] + c[g];
198 66 robfinch 
 
199 
for (g = 0; g < N; g = g + 1)
200 80 robfinch 
        BCDAddAdjust u1 (hsN[g],o[g*4+3:g*4],c[g+1]);
201 66 robfinch 
end
202 
endgenerate
203 
 
204 
endmodule
205 80 robfinch 
*/
206 66 robfinch 
module BCDAddAdjust(i,o,c);
207 
input [4:0] i;
208 
output [3:0] o;
209 
reg [3:0] o;
210 
output c;
211 
reg c;
212 
always @(i)
213 
case(i)
214 
5'h0: begin o = 4'h0; c = 1'b0; end
215 
5'h1: begin o = 4'h1; c = 1'b0; end
216 
5'h2: begin o = 4'h2; c = 1'b0; end
217 
5'h3: begin o = 4'h3; c = 1'b0; end
218 
5'h4: begin o = 4'h4; c = 1'b0; end
219 
5'h5: begin o = 4'h5; c = 1'b0; end
220 
5'h6: begin o = 4'h6; c = 1'b0; end
221 
5'h7: begin o = 4'h7; c = 1'b0; end
222 
5'h8: begin o = 4'h8; c = 1'b0; end
223 
5'h9: begin o = 4'h9; c = 1'b0; end
224 
5'hA: begin o = 4'h0; c = 1'b1; end
225 
5'hB: begin o = 4'h1; c = 1'b1; end
226 
5'hC: begin o = 4'h2; c = 1'b1; end
227 
5'hD: begin o = 4'h3; c = 1'b1; end
228 
5'hE: begin o = 4'h4; c = 1'b1; end
229 
5'hF: begin o = 4'h5; c = 1'b1; end
230 
5'h10:  begin o = 4'h6; c = 1'b1; end
231 
5'h11:  begin o = 4'h7; c = 1'b1; end
232 
5'h12:  begin o = 4'h8; c = 1'b1; end
233 
5'h13:  begin o = 4'h9; c = 1'b1; end
234 
default:        begin o = 4'h9; c = 1'b1; end
235 
endcase
236 
endmodule
237 
 
238 
module BCDSubAdjust(i,o,c);
239 
input [4:0] i;
240 
output [3:0] o;
241 
reg [3:0] o;
242 
output c;
243 
reg c;
244 
always @(i)
245 
case(i)
246 
5'h0: begin o = 4'h0; c = 1'b0; end
247 
5'h1: begin o = 4'h1; c = 1'b0; end
248 
5'h2: begin o = 4'h2; c = 1'b0; end
249 
5'h3: begin o = 4'h3; c = 1'b0; end
250 
5'h4: begin o = 4'h4; c = 1'b0; end
251 
5'h5: begin o = 4'h5; c = 1'b0; end
252 
5'h6: begin o = 4'h6; c = 1'b0; end
253 
5'h7: begin o = 4'h7; c = 1'b0; end
254 
5'h8: begin o = 4'h8; c = 1'b0; end
255 
5'h9: begin o = 4'h9; c = 1'b0; end
256 
5'h16: begin o = 4'h0; c = 1'b1; end
257 
5'h17: begin o = 4'h1; c = 1'b1; end
258 
5'h18: begin o = 4'h2; c = 1'b1; end
259 
5'h19: begin o = 4'h3; c = 1'b1; end
260 
5'h1A: begin o = 4'h4; c = 1'b1; end
261 
5'h1B: begin o = 4'h5; c = 1'b1; end
262 
5'h1C: begin o = 4'h6; c = 1'b1; end
263 
5'h1D: begin o = 4'h7; c = 1'b1; end
264 
5'h1E: begin o = 4'h8; c = 1'b1; end
265 
5'h1F: begin o = 4'h9; c = 1'b1; end
266 
default: begin o = 4'h9; c = 1'b1; end
267 
endcase
268 
endmodule
269 
 
270 
// Multiply two BCD digits
271 
// Method used is table lookup
272 
module BCDMul1(a,b,o);
273 
input [3:0] a;
274 
input [3:0] b;
275 
output [7:0] o;
276 
reg [7:0] o;
277 
 
278 
always @(a or b)
279 
casex({a,b})
280 
8'h00: o = 8'h00;
281 
8'h01: o = 8'h00;
282 
8'h02: o = 8'h00;
283 
8'h03: o = 8'h00;
284 
8'h04: o = 8'h00;
285 
8'h05: o = 8'h00;
286 
8'h06: o = 8'h00;
287 
8'h07: o = 8'h00;
288 
8'h08: o = 8'h00;
289 
8'h09: o = 8'h00;
290 
8'h10: o = 8'h00;
291 
8'h11: o = 8'h01;
292 
8'h12: o = 8'h02;
293 
8'h13: o = 8'h03;
294 
8'h14: o = 8'h04;
295 
8'h15: o = 8'h05;
296 
8'h16: o = 8'h06;
297 
8'h17: o = 8'h07;
298 
8'h18: o = 8'h08;
299 
8'h19: o = 8'h09;
300 
8'h20: o = 8'h00;
301 
8'h21: o = 8'h02;
302 
8'h22: o = 8'h04;
303 
8'h23: o = 8'h06;
304 
8'h24: o = 8'h08;
305 
8'h25: o = 8'h10;
306 
8'h26: o = 8'h12;
307 
8'h27: o = 8'h14;
308 
8'h28: o = 8'h16;
309 
8'h29: o = 8'h18;
310 
8'h30: o = 8'h00;
311 
8'h31: o = 8'h03;
312 
8'h32: o = 8'h06;
313 
8'h33: o = 8'h09;
314 
8'h34: o = 8'h12;
315 
8'h35: o = 8'h15;
316 
8'h36: o = 8'h18;
317 
8'h37: o = 8'h21;
318 
8'h38: o = 8'h24;
319 
8'h39: o = 8'h27;
320 
8'h40: o = 8'h00;
321 
8'h41: o = 8'h04;
322 
8'h42: o = 8'h08;
323 
8'h43: o = 8'h12;
324 
8'h44: o = 8'h16;
325 
8'h45: o = 8'h20;
326 
8'h46: o = 8'h24;
327 
8'h47: o = 8'h28;
328 
8'h48: o = 8'h32;
329 
8'h49: o = 8'h36;
330 
8'h50: o = 8'h00;
331 
8'h51: o = 8'h05;
332 
8'h52: o = 8'h10;
333 
8'h53: o = 8'h15;
334 
8'h54: o = 8'h20;
335 
8'h55: o = 8'h25;
336 
8'h56: o = 8'h30;
337 
8'h57: o = 8'h35;
338 
8'h58: o = 8'h40;
339 
8'h59: o = 8'h45;
340 
8'h60: o = 8'h00;
341 
8'h61: o = 8'h06;
342 
8'h62: o = 8'h12;
343 
8'h63: o = 8'h18;
344 
8'h64: o = 8'h24;
345 
8'h65: o = 8'h30;
346 
8'h66: o = 8'h36;
347 
8'h67: o = 8'h42;
348 
8'h68: o = 8'h48;
349 
8'h69: o = 8'h54;
350 
8'h70: o = 8'h00;
351 
8'h71: o = 8'h07;
352 
8'h72: o = 8'h14;
353 
8'h73: o = 8'h21;
354 
8'h74: o = 8'h28;
355 
8'h75: o = 8'h35;
356 
8'h76: o = 8'h42;
357 
8'h77: o = 8'h49;
358 
8'h78: o = 8'h56;
359 
8'h79: o = 8'h63;
360 
8'h80: o = 8'h00;
361 
8'h81: o = 8'h08;
362 
8'h82: o = 8'h16;
363 
8'h83: o = 8'h24;
364 
8'h84: o = 8'h32;
365 
8'h85: o = 8'h40;
366 
8'h86: o = 8'h48;
367 
8'h87: o = 8'h56;
368 
8'h88: o = 8'h64;
369 
8'h89: o = 8'h72;
370 
8'h90: o = 8'h00;
371 
8'h91: o = 8'h09;
372 
8'h92: o = 8'h18;
373 
8'h93: o = 8'h27;
374 
8'h94: o = 8'h36;
375 
8'h95: o = 8'h45;
376 
8'h96: o = 8'h54;
377 
8'h97: o = 8'h63;
378 
8'h98: o = 8'h72;
379 
8'h99: o = 8'h81;
380 
default:        o = 8'h00;
381 
endcase
382 
endmodule
383 
 
384 
 
385 
// Multiply two pairs of BCD digits
386 
// handles from 0x0 to 99x99
387 
module BCDMul2(a,b,o);
388 
input [7:0] a;
389 
input [7:0] b;
390 
output [15:0] o;
391 
 
392 
wire [7:0] p1,p2,p3,p4;
393 
wire [15:0] s1;
394 
 
395 
BCDMul1 u1 (a[3:0],b[3:0],p1);
396 
BCDMul1 u2 (a[7:4],b[3:0],p2);
397 
BCDMul1 u3 (a[3:0],b[7:4],p3);
398 
BCDMul1 u4 (a[7:4],b[7:4],p4);
399 
 
400 
BCDAdd4 u5 (1'b0,{p4,p1},{4'h0,p2,4'h0},s1);
401 
BCDAdd4 u6 (1'b0,s1,{4'h0,p3,4'h0},o);
402 
 
403 
endmodule
404 
 
405 
module BCDMul4(a,b,o);
406 
input [15:0] a;
407 
input [15:0] b;
408 
output [31:0] o;
409 
 
410 
wire [15:0] p1,p2,p3,p4;
411 
wire [31:0] s1;
412 
 
413 
BCDMul2 u1 (a[7:0],b[7:0],p1);
414 
BCDMul2 u2 (a[15:8],b[7:0],p2);
415 
BCDMul2 u3 (a[7:0],b[15:8],p3);
416 
BCDMul2 u4 (a[15:8],b[15:8],p4);
417 
 
418 
BCDAddN #(.N(8)) u5 (1'b0,{p4,p1},{8'h0,p2,8'h0},s1);
419 
BCDAddN #(.N(8)) u6 (1'b0,s1,{8'h0,p3,8'h0},o);
420 
 
421 
endmodule
422 
 
423 
module BCDMul8(a,b,o);
424 
input [31:0] a;
425 
input [31:0] b;
426 
output [63:0] o;
427 
 
428 
wire [31:0] p1,p2,p3,p4;
429 
wire [63:0] s1;
430 
 
431 
BCDMul4 u1 (a[15:0],b[15:0],p1);
432 
BCDMul4 u2 (a[31:16],b[15:0],p2);
433 
BCDMul4 u3 (a[15:0],b[31:16],p3);
434 
BCDMul4 u4 (a[31:16],b[31:16],p4);
435 
 
436 
BCDAddN #(.N(16)) u5 (1'b0,{p4,p1},{16'h0,p2,16'h0},s1);
437 
BCDAddN #(.N(16)) u6 (1'b0,s1,{16'h0,p3,16'h0},o);
438 
 
439 
endmodule
440 
 
441 
module BCDMul16(a,b,o);
442 
input [63:0] a;
443 
input [63:0] b;
444 
output [127:0] o;
445 
 
446 
wire [63:0] p1,p2,p3,p4;
447 
wire [127:0] s1;
448 
 
449 
BCDMul8 u1 (a[31:0],b[31:0],p1);
450 
BCDMul8 u2 (a[63:32],b[31:0],p2);
451 
BCDMul8 u3 (a[31:0],b[63:32],p3);
452 
BCDMul8 u4 (a[63:32],b[63:32],p4);
453 
 
454 
BCDAddN #(.N(32)) u5 (1'b0,{p4,p1},{32'h0,p2,32'h0},s1);
455 
BCDAddN #(.N(32)) u6 (1'b0,s1,{32'h0,p3,32'h0},o);
456 
 
457 
endmodule
458 
 
459 
module BCDMul32(a,b,o);
460 
input [127:0] a;
461 
input [127:0] b;
462 
output [255:0] o;
463 
 
464 
wire [127:0] p1,p2,p3,p4;
465 
wire [255:0] s1;
466 
 
467 
BCDMul16 u1 (a[63:0],b[63:0],p1);
468 
BCDMul16 u2 (a[127:64],b[63:0],p2);
469 
BCDMul16 u3 (a[63:0],b[127:64],p3);
470 
BCDMul16 u4 (a[127:64],b[127:64],p4);
471 
 
472 
BCDAddN #(.N(64)) u5 (1'b0,{p4,p1},{64'h0,p2,64'h0},s1);
473 
BCDAddN #(.N(64)) u6 (1'b0,s1,{64'h0,p3,64'h0},o);
474 
 
475 
endmodule
476 
 
477 
module BCDMul_tb();
478 
 
479 
wire [15:0] o1,o2,o3,o4;
480 
 
481 
BCDMul2 u1 (8'h00,8'h00,o1);
482 
BCDMul2 u2 (8'h99,8'h99,o2);
483 
BCDMul2 u3 (8'h25,8'h18,o3);
484 
BCDMul2 u4 (8'h37,8'h21,o4);
485 
 
486 
endmodule
487 
 
488 
module BinToBCD(i, o);
489 
input [7:0] i;
490 
output [11:0] o;
491 
 
492 
reg [11:0] tbl [0:255];
493 
 
494 
genvar g;
495 
generate begin : gTbl
496 
reg [3:0] n0 [0:255];
497 
reg [3:0] n1 [0:255];
498 
reg [3:0] n2 [0:255];
499 
 
500 
for (g = 0; g < 256; g = g + 1) begin
501 
        initial begin
502 
                n0[g] = g % 10;
503 
                n1[g] = g / 10;
504 
                n2[g] = g / 100;
505 
                tbl[g] <= {n2[g],n1[g],n0[g]};
506 
        end
507 
end
508 
 
509 
assign o = tbl[i];
510 
 
511 
end
512 
endgenerate
513 
 
514 
endmodule
515 
 
516 
// Perform a logical shift to the right.
517 
module BCDSRL(ci, i, o, co);
518 
parameter N=4;
519 
input ci;
520 
input [N*4-1:0] i;
521 
output reg [N*4-1:0] o;
522 
output co;
523 
 
524 
reg [N:0] c;
525 
 
526 
genvar g;
527 
generate begin
528 
always @*
529 
        c[N] = ci;
530 
for (g = N - 1; g >= 0; g = g - 1)
531 
always @*
532 
        c[g] = i[g*4];
533 
for (g = N - 1; g >= 0; g = g - 1)
534 
always @*
535 
begin
536 
        o[g*4+3:g*4] = {1'b0,i[g*4+3:g*4+1]};
537 
        // Because there is a divide by two, the value will range between 0 and 4.
538 
        // Adding 5 keeps it within deicmal boundaries of 0 to 9. No carry can be
539 
        // generated
540 
        if (c[N+1])
541 
                o[g*4+3:g*4] = o[g*4+3:g*4] + 4'd5;
542 
end
543 
        assign co = c[0];
544 
end
545 
endgenerate
546 
 
547 
endmodule

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