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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2012-2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// BCDMath.sv
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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module BCDAdd(ci,a,b,o,c);
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input ci; // carry input
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input [7:0] a;
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input [7:0] b;
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output [7:0] o;
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output c;
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wire c0,c1;
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wire [4:0] hsN0 = a[3:0] + b[3:0] + ci;
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wire [4:0] hsN1 = a[7:4] + b[7:4] + c0;
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BCDAddAdjust u1 (hsN0,o[3:0],c0);
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BCDAddAdjust u2 (hsN1,o[7:4],c);
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endmodule
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module BCDAdd4(ci,a,b,o,c,c8);
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input ci; // carry input
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input [15:0] a;
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input [15:0] b;
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output [15:0] o;
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output c;
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output c8;
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wire c0,c1,c2;
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assign c8 = c1;
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wire [4:0] hsN0 = a[3:0] + b[3:0] + ci;
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wire [4:0] hsN1 = a[7:4] + b[7:4] + c0;
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wire [4:0] hsN2 = a[11:8] + b[11:8] + c1;
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wire [4:0] hsN3 = a[15:12] + b[15:12] + c2;
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BCDAddAdjust u1 (hsN0,o[3:0],c0);
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BCDAddAdjust u2 (hsN1,o[7:4],c1);
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BCDAddAdjust u3 (hsN2,o[11:8],c2);
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BCDAddAdjust u4 (hsN3,o[15:12],c);
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endmodule
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module BCDAddN(ci,a,b,o,co);
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parameter N=24;
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input ci; // carry input
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input [N*4-1:0] a;
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input [N*4-1:0] b;
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output [N*4-1:0] o;
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output co;
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genvar g;
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generate begin : gBCDAddN
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reg [4:0] hsN [0:N-1];
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wire [N:0] c;
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assign c[0] = ci;
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assign co = c[N];
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for (g = 0; g < N; g = g + 1)
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always @*
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hsN[g] = a[g*4+3:g*4] + b[g*4+3:g*4] + c[g];
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for (g = 0; g < N; g = g + 1)
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BCDAddAdjust u1 (hsN[g],o[g*4+3:g*4],c[g+1]);
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end
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endgenerate
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endmodule
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module BCDSub(ci,a,b,o,c);
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input ci; // carry input
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input [7:0] a;
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input [7:0] b;
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output [7:0] o;
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output c;
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wire c0,c1;
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wire [4:0] hdN0 = a[3:0] - b[3:0] - ci;
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wire [4:0] hdN1 = a[7:4] - b[7:4] - c0;
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BCDSubAdjust u1 (hdN0,o[3:0],c0);
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BCDSubAdjust u2 (hdN1,o[7:4],c);
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endmodule
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module BCDSub4(ci,a,b,o,c,c8);
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input ci; // carry input
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input [15:0] a;
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input [15:0] b;
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output [15:0] o;
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output c;
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output c8;
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wire c0,c1,c2;
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assign c8 = c1;
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wire [4:0] hdN0 = a[3:0] - b[3:0] - ci;
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wire [4:0] hdN1 = a[7:4] - b[7:4] - c0;
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wire [4:0] hdN2 = a[11:8] - b[11:8] - c1;
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wire [4:0] hdN3 = a[15:12] - b[15:12] - c2;
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BCDSubAdjust u1 (hdN0,o[3:0],c0);
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BCDSubAdjust u2 (hdN1,o[7:4],c1);
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BCDSubAdjust u3 (hdN2,o[11:8],c2);
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BCDSubAdjust u4 (hdN3,o[15:12],c);
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endmodule
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module BCDSubN(ci,a,b,o,co);
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parameter N=24;
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input ci; // carry input
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input [N*4-1:0] a;
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input [N*4-1:0] b;
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output [N*4-1:0] o;
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output co;
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genvar g;
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generate begin : gBCDSubN
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reg [4:0] hdN [0:N-1];
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wire [N:0] c;
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assign c[0] = ci;
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assign co = c[N];
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for (g = 0; g < N; g = g + 1)
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always @*
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hdN[g] = a[g*4+3:g*4] - b[g*4+3:g*4] - c[g];
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for (g = 0; g < N; g = g + 1)
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BCDSubAdjust u1 (hdN[g],o[g*4+3:g*4],c[g+1]);
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end
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endgenerate
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endmodule
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module BCDAddAdjust(i,o,c);
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input [4:0] i;
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output [3:0] o;
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reg [3:0] o;
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output c;
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reg c;
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always @(i)
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case(i)
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5'h0: begin o = 4'h0; c = 1'b0; end
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5'h1: begin o = 4'h1; c = 1'b0; end
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5'h2: begin o = 4'h2; c = 1'b0; end
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5'h3: begin o = 4'h3; c = 1'b0; end
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5'h4: begin o = 4'h4; c = 1'b0; end
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5'h5: begin o = 4'h5; c = 1'b0; end
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5'h6: begin o = 4'h6; c = 1'b0; end
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5'h7: begin o = 4'h7; c = 1'b0; end
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5'h8: begin o = 4'h8; c = 1'b0; end
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5'h9: begin o = 4'h9; c = 1'b0; end
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5'hA: begin o = 4'h0; c = 1'b1; end
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5'hB: begin o = 4'h1; c = 1'b1; end
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5'hC: begin o = 4'h2; c = 1'b1; end
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5'hD: begin o = 4'h3; c = 1'b1; end
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5'hE: begin o = 4'h4; c = 1'b1; end
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5'hF: begin o = 4'h5; c = 1'b1; end
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5'h10: begin o = 4'h6; c = 1'b1; end
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5'h11: begin o = 4'h7; c = 1'b1; end
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5'h12: begin o = 4'h8; c = 1'b1; end
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5'h13: begin o = 4'h9; c = 1'b1; end
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default: begin o = 4'h9; c = 1'b1; end
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endcase
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endmodule
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module BCDSubAdjust(i,o,c);
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input [4:0] i;
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output [3:0] o;
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reg [3:0] o;
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output c;
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reg c;
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always @(i)
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case(i)
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5'h0: begin o = 4'h0; c = 1'b0; end
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5'h1: begin o = 4'h1; c = 1'b0; end
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5'h2: begin o = 4'h2; c = 1'b0; end
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5'h3: begin o = 4'h3; c = 1'b0; end
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5'h4: begin o = 4'h4; c = 1'b0; end
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5'h5: begin o = 4'h5; c = 1'b0; end
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5'h6: begin o = 4'h6; c = 1'b0; end
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5'h7: begin o = 4'h7; c = 1'b0; end
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5'h8: begin o = 4'h8; c = 1'b0; end
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5'h9: begin o = 4'h9; c = 1'b0; end
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5'h16: begin o = 4'h0; c = 1'b1; end
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5'h17: begin o = 4'h1; c = 1'b1; end
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5'h18: begin o = 4'h2; c = 1'b1; end
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5'h19: begin o = 4'h3; c = 1'b1; end
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5'h1A: begin o = 4'h4; c = 1'b1; end
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5'h1B: begin o = 4'h5; c = 1'b1; end
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5'h1C: begin o = 4'h6; c = 1'b1; end
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5'h1D: begin o = 4'h7; c = 1'b1; end
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5'h1E: begin o = 4'h8; c = 1'b1; end
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5'h1F: begin o = 4'h9; c = 1'b1; end
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default: begin o = 4'h9; c = 1'b1; end
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endcase
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endmodule
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// Multiply two BCD digits
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// Method used is table lookup
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module BCDMul1(a,b,o);
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input [3:0] a;
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input [3:0] b;
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output [7:0] o;
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reg [7:0] o;
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always @(a or b)
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casex({a,b})
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8'h00: o = 8'h00;
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8'h01: o = 8'h00;
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8'h02: o = 8'h00;
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8'h03: o = 8'h00;
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8'h04: o = 8'h00;
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8'h05: o = 8'h00;
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8'h06: o = 8'h00;
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8'h07: o = 8'h00;
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8'h08: o = 8'h00;
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8'h09: o = 8'h00;
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8'h10: o = 8'h00;
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8'h11: o = 8'h01;
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8'h12: o = 8'h02;
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8'h13: o = 8'h03;
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8'h14: o = 8'h04;
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8'h15: o = 8'h05;
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8'h16: o = 8'h06;
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8'h17: o = 8'h07;
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8'h18: o = 8'h08;
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8'h19: o = 8'h09;
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8'h20: o = 8'h00;
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8'h21: o = 8'h02;
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8'h22: o = 8'h04;
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8'h23: o = 8'h06;
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8'h24: o = 8'h08;
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8'h25: o = 8'h10;
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8'h26: o = 8'h12;
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8'h27: o = 8'h14;
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8'h28: o = 8'h16;
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8'h29: o = 8'h18;
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8'h30: o = 8'h00;
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8'h31: o = 8'h03;
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8'h32: o = 8'h06;
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8'h33: o = 8'h09;
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8'h34: o = 8'h12;
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8'h35: o = 8'h15;
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8'h36: o = 8'h18;
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8'h37: o = 8'h21;
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8'h38: o = 8'h24;
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8'h39: o = 8'h27;
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8'h40: o = 8'h00;
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8'h41: o = 8'h04;
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8'h42: o = 8'h08;
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8'h43: o = 8'h12;
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8'h44: o = 8'h16;
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8'h45: o = 8'h20;
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8'h46: o = 8'h24;
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8'h47: o = 8'h28;
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8'h48: o = 8'h32;
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8'h49: o = 8'h36;
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8'h50: o = 8'h00;
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8'h51: o = 8'h05;
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8'h52: o = 8'h10;
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8'h53: o = 8'h15;
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8'h54: o = 8'h20;
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8'h55: o = 8'h25;
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8'h56: o = 8'h30;
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8'h57: o = 8'h35;
|
| 305 |
|
|
8'h58: o = 8'h40;
|
| 306 |
|
|
8'h59: o = 8'h45;
|
| 307 |
|
|
8'h60: o = 8'h00;
|
| 308 |
|
|
8'h61: o = 8'h06;
|
| 309 |
|
|
8'h62: o = 8'h12;
|
| 310 |
|
|
8'h63: o = 8'h18;
|
| 311 |
|
|
8'h64: o = 8'h24;
|
| 312 |
|
|
8'h65: o = 8'h30;
|
| 313 |
|
|
8'h66: o = 8'h36;
|
| 314 |
|
|
8'h67: o = 8'h42;
|
| 315 |
|
|
8'h68: o = 8'h48;
|
| 316 |
|
|
8'h69: o = 8'h54;
|
| 317 |
|
|
8'h70: o = 8'h00;
|
| 318 |
|
|
8'h71: o = 8'h07;
|
| 319 |
|
|
8'h72: o = 8'h14;
|
| 320 |
|
|
8'h73: o = 8'h21;
|
| 321 |
|
|
8'h74: o = 8'h28;
|
| 322 |
|
|
8'h75: o = 8'h35;
|
| 323 |
|
|
8'h76: o = 8'h42;
|
| 324 |
|
|
8'h77: o = 8'h49;
|
| 325 |
|
|
8'h78: o = 8'h56;
|
| 326 |
|
|
8'h79: o = 8'h63;
|
| 327 |
|
|
8'h80: o = 8'h00;
|
| 328 |
|
|
8'h81: o = 8'h08;
|
| 329 |
|
|
8'h82: o = 8'h16;
|
| 330 |
|
|
8'h83: o = 8'h24;
|
| 331 |
|
|
8'h84: o = 8'h32;
|
| 332 |
|
|
8'h85: o = 8'h40;
|
| 333 |
|
|
8'h86: o = 8'h48;
|
| 334 |
|
|
8'h87: o = 8'h56;
|
| 335 |
|
|
8'h88: o = 8'h64;
|
| 336 |
|
|
8'h89: o = 8'h72;
|
| 337 |
|
|
8'h90: o = 8'h00;
|
| 338 |
|
|
8'h91: o = 8'h09;
|
| 339 |
|
|
8'h92: o = 8'h18;
|
| 340 |
|
|
8'h93: o = 8'h27;
|
| 341 |
|
|
8'h94: o = 8'h36;
|
| 342 |
|
|
8'h95: o = 8'h45;
|
| 343 |
|
|
8'h96: o = 8'h54;
|
| 344 |
|
|
8'h97: o = 8'h63;
|
| 345 |
|
|
8'h98: o = 8'h72;
|
| 346 |
|
|
8'h99: o = 8'h81;
|
| 347 |
|
|
default: o = 8'h00;
|
| 348 |
|
|
endcase
|
| 349 |
|
|
endmodule
|
| 350 |
|
|
|
| 351 |
|
|
|
| 352 |
|
|
// Multiply two pairs of BCD digits
|
| 353 |
|
|
// handles from 0x0 to 99x99
|
| 354 |
|
|
module BCDMul2(a,b,o);
|
| 355 |
|
|
input [7:0] a;
|
| 356 |
|
|
input [7:0] b;
|
| 357 |
|
|
output [15:0] o;
|
| 358 |
|
|
|
| 359 |
|
|
wire [7:0] p1,p2,p3,p4;
|
| 360 |
|
|
wire [15:0] s1;
|
| 361 |
|
|
|
| 362 |
|
|
BCDMul1 u1 (a[3:0],b[3:0],p1);
|
| 363 |
|
|
BCDMul1 u2 (a[7:4],b[3:0],p2);
|
| 364 |
|
|
BCDMul1 u3 (a[3:0],b[7:4],p3);
|
| 365 |
|
|
BCDMul1 u4 (a[7:4],b[7:4],p4);
|
| 366 |
|
|
|
| 367 |
|
|
BCDAdd4 u5 (1'b0,{p4,p1},{4'h0,p2,4'h0},s1);
|
| 368 |
|
|
BCDAdd4 u6 (1'b0,s1,{4'h0,p3,4'h0},o);
|
| 369 |
|
|
|
| 370 |
|
|
endmodule
|
| 371 |
|
|
|
| 372 |
|
|
module BCDMul_tb();
|
| 373 |
|
|
|
| 374 |
|
|
wire [15:0] o1,o2,o3,o4;
|
| 375 |
|
|
|
| 376 |
|
|
BCDMul2 u1 (8'h00,8'h00,o1);
|
| 377 |
|
|
BCDMul2 u2 (8'h99,8'h99,o2);
|
| 378 |
|
|
BCDMul2 u3 (8'h25,8'h18,o3);
|
| 379 |
|
|
BCDMul2 u4 (8'h37,8'h21,o4);
|
| 380 |
|
|
|
| 381 |
|
|
endmodule
|
| 382 |
|
|
|
| 383 |
|
|
module BinToBCD(i, o);
|
| 384 |
|
|
input [7:0] i;
|
| 385 |
|
|
output [11:0] o;
|
| 386 |
|
|
|
| 387 |
|
|
reg [11:0] tbl [0:255];
|
| 388 |
|
|
|
| 389 |
|
|
genvar g;
|
| 390 |
|
|
generate begin : gTbl
|
| 391 |
|
|
reg [3:0] n0 [0:255];
|
| 392 |
|
|
reg [3:0] n1 [0:255];
|
| 393 |
|
|
reg [3:0] n2 [0:255];
|
| 394 |
|
|
|
| 395 |
|
|
for (g = 0; g < 256; g = g + 1) begin
|
| 396 |
|
|
initial begin
|
| 397 |
|
|
n0[g] = g % 10;
|
| 398 |
|
|
n1[g] = g / 10;
|
| 399 |
|
|
n2[g] = g / 100;
|
| 400 |
|
|
tbl[g] <= {n2[g],n1[g],n0[g]};
|
| 401 |
|
|
end
|
| 402 |
|
|
end
|
| 403 |
|
|
|
| 404 |
|
|
assign o = tbl[i];
|
| 405 |
|
|
|
| 406 |
|
|
end
|
| 407 |
|
|
endgenerate
|
| 408 |
|
|
|
| 409 |
|
|
endmodule
|
