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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [BCDMath.v] - Blame information for rev 56

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1 50 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2012-2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
7
//       ||
8
//
9
//      BCDMath.sv
10
//
11
// BSD 3-Clause License
12
// Redistribution and use in source and binary forms, with or without
13
// modification, are permitted provided that the following conditions are met:
14
//
15
// 1. Redistributions of source code must retain the above copyright notice, this
16
//    list of conditions and the following disclaimer.
17
//
18
// 2. Redistributions in binary form must reproduce the above copyright notice,
19
//    this list of conditions and the following disclaimer in the documentation
20
//    and/or other materials provided with the distribution.
21
//
22
// 3. Neither the name of the copyright holder nor the names of its
23
//    contributors may be used to endorse or promote products derived from
24
//    this software without specific prior written permission.
25
//
26
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
30
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
33
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36
//                                                                          
37
// ============================================================================
38
//
39 54 robfinch
// Could use the following approach for add/sub but it ends up being larger
40
// than using an adjustment lookup table.
41
 
42
module BCDAddNyb(ci,a,b,o,c);
43
input ci;               // carry input
44
input [3:0] a;
45
input [3:0] b;
46
output [3:0] o;
47
output c;
48
 
49
wire c0;
50
 
51
reg [4:0] hsN0;
52
always  @*
53
begin
54
        hsN0 = a[3:0] + b[3:0] + ci;
55
        if (hsN0 > 5'd9)
56
                hsN0 = hsN0 + 3'd6;
57
end
58
assign o = hsN0[3:0];
59
assign c = hsN0[4];
60
 
61
endmodule
62
 
63 50 robfinch
module BCDAdd(ci,a,b,o,c);
64
input ci;               // carry input
65
input [7:0] a;
66
input [7:0] b;
67
output [7:0] o;
68
output c;
69
 
70
wire c0,c1;
71
 
72
wire [4:0] hsN0 = a[3:0] + b[3:0] + ci;
73
wire [4:0] hsN1 = a[7:4] + b[7:4] + c0;
74
 
75
BCDAddAdjust u1 (hsN0,o[3:0],c0);
76
BCDAddAdjust u2 (hsN1,o[7:4],c);
77
 
78
endmodule
79
 
80
module BCDAdd4(ci,a,b,o,c,c8);
81
input ci;               // carry input
82
input [15:0] a;
83
input [15:0] b;
84
output [15:0] o;
85
output c;
86
output c8;
87
 
88
wire c0,c1,c2;
89
assign c8 = c1;
90
 
91
wire [4:0] hsN0 = a[3:0] + b[3:0] + ci;
92
wire [4:0] hsN1 = a[7:4] + b[7:4] + c0;
93
wire [4:0] hsN2 = a[11:8] + b[11:8] + c1;
94
wire [4:0] hsN3 = a[15:12] + b[15:12] + c2;
95
 
96
BCDAddAdjust u1 (hsN0,o[3:0],c0);
97
BCDAddAdjust u2 (hsN1,o[7:4],c1);
98
BCDAddAdjust u3 (hsN2,o[11:8],c2);
99
BCDAddAdjust u4 (hsN3,o[15:12],c);
100
 
101
endmodule
102
 
103
module BCDAddN(ci,a,b,o,co);
104
parameter N=24;
105
input ci;               // carry input
106
input [N*4-1:0] a;
107
input [N*4-1:0] b;
108
output [N*4-1:0] o;
109
output co;
110
 
111
genvar g;
112
generate begin : gBCDAddN
113
reg [4:0] hsN [0:N-1];
114
wire [N:0] c;
115
 
116
assign c[0] = ci;
117
assign co = c[N];
118
 
119
for (g = 0; g < N; g = g + 1)
120
        always @*
121
                hsN[g] = a[g*4+3:g*4] + b[g*4+3:g*4] + c[g];
122
 
123
for (g = 0; g < N; g = g + 1)
124
        BCDAddAdjust u1 (hsN[g],o[g*4+3:g*4],c[g+1]);
125
end
126
endgenerate
127
 
128
endmodule
129
 
130
module BCDSub(ci,a,b,o,c);
131
input ci;               // carry input
132
input [7:0] a;
133
input [7:0] b;
134
output [7:0] o;
135
output c;
136
 
137
wire c0,c1;
138
 
139
wire [4:0] hdN0 = a[3:0] - b[3:0] - ci;
140
wire [4:0] hdN1 = a[7:4] - b[7:4] - c0;
141
 
142
BCDSubAdjust u1 (hdN0,o[3:0],c0);
143
BCDSubAdjust u2 (hdN1,o[7:4],c);
144
 
145
endmodule
146
 
147
module BCDSub4(ci,a,b,o,c,c8);
148
input ci;               // carry input
149
input [15:0] a;
150
input [15:0] b;
151
output [15:0] o;
152
output c;
153
output c8;
154
 
155
wire c0,c1,c2;
156
assign c8 = c1;
157
 
158
wire [4:0] hdN0 = a[3:0] - b[3:0] - ci;
159
wire [4:0] hdN1 = a[7:4] - b[7:4] - c0;
160
wire [4:0] hdN2 = a[11:8] - b[11:8] - c1;
161
wire [4:0] hdN3 = a[15:12] - b[15:12] - c2;
162
 
163
BCDSubAdjust u1 (hdN0,o[3:0],c0);
164
BCDSubAdjust u2 (hdN1,o[7:4],c1);
165
BCDSubAdjust u3 (hdN2,o[11:8],c2);
166
BCDSubAdjust u4 (hdN3,o[15:12],c);
167
 
168
endmodule
169
 
170
module BCDSubN(ci,a,b,o,co);
171
parameter N=24;
172
input ci;               // carry input
173
input [N*4-1:0] a;
174
input [N*4-1:0] b;
175
output [N*4-1:0] o;
176
output co;
177
 
178
genvar g;
179
generate begin : gBCDSubN
180
reg [4:0] hdN [0:N-1];
181
wire [N:0] c;
182
 
183
assign c[0] = ci;
184
assign co = c[N];
185
 
186
for (g = 0; g < N; g = g + 1)
187
        always @*
188
                hdN[g] = a[g*4+3:g*4] - b[g*4+3:g*4] - c[g];
189
 
190
for (g = 0; g < N; g = g + 1)
191
        BCDSubAdjust u1 (hdN[g],o[g*4+3:g*4],c[g+1]);
192
end
193
endgenerate
194
 
195
endmodule
196
 
197
module BCDAddAdjust(i,o,c);
198
input [4:0] i;
199
output [3:0] o;
200
reg [3:0] o;
201
output c;
202
reg c;
203
always @(i)
204
case(i)
205
5'h0: begin o = 4'h0; c = 1'b0; end
206
5'h1: begin o = 4'h1; c = 1'b0; end
207
5'h2: begin o = 4'h2; c = 1'b0; end
208
5'h3: begin o = 4'h3; c = 1'b0; end
209
5'h4: begin o = 4'h4; c = 1'b0; end
210
5'h5: begin o = 4'h5; c = 1'b0; end
211
5'h6: begin o = 4'h6; c = 1'b0; end
212
5'h7: begin o = 4'h7; c = 1'b0; end
213
5'h8: begin o = 4'h8; c = 1'b0; end
214
5'h9: begin o = 4'h9; c = 1'b0; end
215
5'hA: begin o = 4'h0; c = 1'b1; end
216
5'hB: begin o = 4'h1; c = 1'b1; end
217
5'hC: begin o = 4'h2; c = 1'b1; end
218
5'hD: begin o = 4'h3; c = 1'b1; end
219
5'hE: begin o = 4'h4; c = 1'b1; end
220
5'hF: begin o = 4'h5; c = 1'b1; end
221
5'h10:  begin o = 4'h6; c = 1'b1; end
222
5'h11:  begin o = 4'h7; c = 1'b1; end
223
5'h12:  begin o = 4'h8; c = 1'b1; end
224
5'h13:  begin o = 4'h9; c = 1'b1; end
225
default:        begin o = 4'h9; c = 1'b1; end
226
endcase
227
endmodule
228
 
229
module BCDSubAdjust(i,o,c);
230
input [4:0] i;
231
output [3:0] o;
232
reg [3:0] o;
233
output c;
234
reg c;
235
always @(i)
236
case(i)
237
5'h0: begin o = 4'h0; c = 1'b0; end
238
5'h1: begin o = 4'h1; c = 1'b0; end
239
5'h2: begin o = 4'h2; c = 1'b0; end
240
5'h3: begin o = 4'h3; c = 1'b0; end
241
5'h4: begin o = 4'h4; c = 1'b0; end
242
5'h5: begin o = 4'h5; c = 1'b0; end
243
5'h6: begin o = 4'h6; c = 1'b0; end
244
5'h7: begin o = 4'h7; c = 1'b0; end
245
5'h8: begin o = 4'h8; c = 1'b0; end
246
5'h9: begin o = 4'h9; c = 1'b0; end
247
5'h16: begin o = 4'h0; c = 1'b1; end
248
5'h17: begin o = 4'h1; c = 1'b1; end
249
5'h18: begin o = 4'h2; c = 1'b1; end
250
5'h19: begin o = 4'h3; c = 1'b1; end
251
5'h1A: begin o = 4'h4; c = 1'b1; end
252
5'h1B: begin o = 4'h5; c = 1'b1; end
253
5'h1C: begin o = 4'h6; c = 1'b1; end
254
5'h1D: begin o = 4'h7; c = 1'b1; end
255
5'h1E: begin o = 4'h8; c = 1'b1; end
256
5'h1F: begin o = 4'h9; c = 1'b1; end
257
default: begin o = 4'h9; c = 1'b1; end
258
endcase
259
endmodule
260
 
261
// Multiply two BCD digits
262
// Method used is table lookup
263
module BCDMul1(a,b,o);
264
input [3:0] a;
265
input [3:0] b;
266
output [7:0] o;
267
reg [7:0] o;
268
 
269
always @(a or b)
270
casex({a,b})
271
8'h00: o = 8'h00;
272
8'h01: o = 8'h00;
273
8'h02: o = 8'h00;
274
8'h03: o = 8'h00;
275
8'h04: o = 8'h00;
276
8'h05: o = 8'h00;
277
8'h06: o = 8'h00;
278
8'h07: o = 8'h00;
279
8'h08: o = 8'h00;
280
8'h09: o = 8'h00;
281
8'h10: o = 8'h00;
282
8'h11: o = 8'h01;
283
8'h12: o = 8'h02;
284
8'h13: o = 8'h03;
285
8'h14: o = 8'h04;
286
8'h15: o = 8'h05;
287
8'h16: o = 8'h06;
288
8'h17: o = 8'h07;
289
8'h18: o = 8'h08;
290
8'h19: o = 8'h09;
291
8'h20: o = 8'h00;
292
8'h21: o = 8'h02;
293
8'h22: o = 8'h04;
294
8'h23: o = 8'h06;
295
8'h24: o = 8'h08;
296
8'h25: o = 8'h10;
297
8'h26: o = 8'h12;
298
8'h27: o = 8'h14;
299
8'h28: o = 8'h16;
300
8'h29: o = 8'h18;
301
8'h30: o = 8'h00;
302
8'h31: o = 8'h03;
303
8'h32: o = 8'h06;
304
8'h33: o = 8'h09;
305
8'h34: o = 8'h12;
306
8'h35: o = 8'h15;
307
8'h36: o = 8'h18;
308
8'h37: o = 8'h21;
309
8'h38: o = 8'h24;
310
8'h39: o = 8'h27;
311
8'h40: o = 8'h00;
312
8'h41: o = 8'h04;
313
8'h42: o = 8'h08;
314
8'h43: o = 8'h12;
315
8'h44: o = 8'h16;
316
8'h45: o = 8'h20;
317
8'h46: o = 8'h24;
318
8'h47: o = 8'h28;
319
8'h48: o = 8'h32;
320
8'h49: o = 8'h36;
321
8'h50: o = 8'h00;
322
8'h51: o = 8'h05;
323
8'h52: o = 8'h10;
324
8'h53: o = 8'h15;
325
8'h54: o = 8'h20;
326
8'h55: o = 8'h25;
327
8'h56: o = 8'h30;
328
8'h57: o = 8'h35;
329
8'h58: o = 8'h40;
330
8'h59: o = 8'h45;
331
8'h60: o = 8'h00;
332
8'h61: o = 8'h06;
333
8'h62: o = 8'h12;
334
8'h63: o = 8'h18;
335
8'h64: o = 8'h24;
336
8'h65: o = 8'h30;
337
8'h66: o = 8'h36;
338
8'h67: o = 8'h42;
339
8'h68: o = 8'h48;
340
8'h69: o = 8'h54;
341
8'h70: o = 8'h00;
342
8'h71: o = 8'h07;
343
8'h72: o = 8'h14;
344
8'h73: o = 8'h21;
345
8'h74: o = 8'h28;
346
8'h75: o = 8'h35;
347
8'h76: o = 8'h42;
348
8'h77: o = 8'h49;
349
8'h78: o = 8'h56;
350
8'h79: o = 8'h63;
351
8'h80: o = 8'h00;
352
8'h81: o = 8'h08;
353
8'h82: o = 8'h16;
354
8'h83: o = 8'h24;
355
8'h84: o = 8'h32;
356
8'h85: o = 8'h40;
357
8'h86: o = 8'h48;
358
8'h87: o = 8'h56;
359
8'h88: o = 8'h64;
360
8'h89: o = 8'h72;
361
8'h90: o = 8'h00;
362
8'h91: o = 8'h09;
363
8'h92: o = 8'h18;
364
8'h93: o = 8'h27;
365
8'h94: o = 8'h36;
366
8'h95: o = 8'h45;
367
8'h96: o = 8'h54;
368
8'h97: o = 8'h63;
369
8'h98: o = 8'h72;
370
8'h99: o = 8'h81;
371
default:        o = 8'h00;
372
endcase
373
endmodule
374
 
375
 
376
// Multiply two pairs of BCD digits
377
// handles from 0x0 to 99x99
378
module BCDMul2(a,b,o);
379
input [7:0] a;
380
input [7:0] b;
381
output [15:0] o;
382
 
383
wire [7:0] p1,p2,p3,p4;
384
wire [15:0] s1;
385
 
386
BCDMul1 u1 (a[3:0],b[3:0],p1);
387
BCDMul1 u2 (a[7:4],b[3:0],p2);
388
BCDMul1 u3 (a[3:0],b[7:4],p3);
389
BCDMul1 u4 (a[7:4],b[7:4],p4);
390
 
391
BCDAdd4 u5 (1'b0,{p4,p1},{4'h0,p2,4'h0},s1);
392
BCDAdd4 u6 (1'b0,s1,{4'h0,p3,4'h0},o);
393
 
394
endmodule
395
 
396 53 robfinch
module BCDMul4(a,b,o);
397
input [15:0] a;
398
input [15:0] b;
399
output [31:0] o;
400
 
401
wire [15:0] p1,p2,p3,p4;
402
wire [31:0] s1;
403
 
404
BCDMul2 u1 (a[7:0],b[7:0],p1);
405
BCDMul2 u2 (a[15:8],b[7:0],p2);
406
BCDMul2 u3 (a[7:0],b[15:8],p3);
407
BCDMul2 u4 (a[15:8],b[15:8],p4);
408
 
409
BCDAddN #(.N(8)) u5 (1'b0,{p4,p1},{8'h0,p2,8'h0},s1);
410
BCDAddN #(.N(8)) u6 (1'b0,s1,{8'h0,p3,8'h0},o);
411
 
412
endmodule
413
 
414
module BCDMul8(a,b,o);
415
input [31:0] a;
416
input [31:0] b;
417
output [63:0] o;
418
 
419
wire [31:0] p1,p2,p3,p4;
420
wire [63:0] s1;
421
 
422
BCDMul4 u1 (a[15:0],b[15:0],p1);
423
BCDMul4 u2 (a[31:16],b[15:0],p2);
424
BCDMul4 u3 (a[15:0],b[31:16],p3);
425
BCDMul4 u4 (a[31:16],b[31:16],p4);
426
 
427
BCDAddN #(.N(16)) u5 (1'b0,{p4,p1},{16'h0,p2,16'h0},s1);
428
BCDAddN #(.N(16)) u6 (1'b0,s1,{16'h0,p3,16'h0},o);
429
 
430
endmodule
431
 
432
module BCDMul16(a,b,o);
433
input [63:0] a;
434
input [63:0] b;
435
output [127:0] o;
436
 
437
wire [63:0] p1,p2,p3,p4;
438
wire [127:0] s1;
439
 
440
BCDMul8 u1 (a[31:0],b[31:0],p1);
441
BCDMul8 u2 (a[63:32],b[31:0],p2);
442
BCDMul8 u3 (a[31:0],b[63:32],p3);
443
BCDMul8 u4 (a[63:32],b[63:32],p4);
444
 
445
BCDAddN #(.N(32)) u5 (1'b0,{p4,p1},{32'h0,p2,32'h0},s1);
446
BCDAddN #(.N(32)) u6 (1'b0,s1,{32'h0,p3,32'h0},o);
447
 
448
endmodule
449
 
450
module BCDMul32(a,b,o);
451
input [127:0] a;
452
input [127:0] b;
453
output [255:0] o;
454
 
455
wire [127:0] p1,p2,p3,p4;
456
wire [255:0] s1;
457
 
458
BCDMul16 u1 (a[63:0],b[63:0],p1);
459
BCDMul16 u2 (a[127:64],b[63:0],p2);
460
BCDMul16 u3 (a[63:0],b[127:64],p3);
461
BCDMul16 u4 (a[127:64],b[127:64],p4);
462
 
463
BCDAddN #(.N(64)) u5 (1'b0,{p4,p1},{64'h0,p2,64'h0},s1);
464
BCDAddN #(.N(64)) u6 (1'b0,s1,{64'h0,p3,64'h0},o);
465
 
466
endmodule
467
 
468 50 robfinch
module BCDMul_tb();
469
 
470
wire [15:0] o1,o2,o3,o4;
471
 
472
BCDMul2 u1 (8'h00,8'h00,o1);
473
BCDMul2 u2 (8'h99,8'h99,o2);
474
BCDMul2 u3 (8'h25,8'h18,o3);
475
BCDMul2 u4 (8'h37,8'h21,o4);
476
 
477
endmodule
478
 
479
module BinToBCD(i, o);
480
input [7:0] i;
481
output [11:0] o;
482
 
483
reg [11:0] tbl [0:255];
484
 
485
genvar g;
486
generate begin : gTbl
487
reg [3:0] n0 [0:255];
488
reg [3:0] n1 [0:255];
489
reg [3:0] n2 [0:255];
490
 
491
for (g = 0; g < 256; g = g + 1) begin
492
        initial begin
493
                n0[g] = g % 10;
494
                n1[g] = g / 10;
495
                n2[g] = g / 100;
496
                tbl[g] <= {n2[g],n1[g],n0[g]};
497
        end
498
end
499
 
500
assign o = tbl[i];
501
 
502
end
503
endgenerate
504
 
505
endmodule
506 56 robfinch
 
507
// Perform a logical shift to the right.
508
module BCDSRL(ci, i, o, co);
509
parameter N=4;
510
input ci;
511
input [N*4-1:0] i;
512
output reg [N*4-1:0] o;
513
output co;
514
 
515
reg [N:0] c;
516
 
517
genvar g;
518
generate begin
519
always @*
520
        c[N] = ci;
521
for (g = N - 1; g >= 0; g = g - 1)
522
always @*
523
        c[g] = i[g*4];
524
for (g = N - 1; g >= 0; g = g - 1)
525
always @*
526
begin
527
        o[g*4+3:g*4] = {1'b0,i[g*4+3:g*4+1]};
528
        // Because there is a divide by two, the value will range between 0 and 4.
529
        // Adding 5 keeps it within deicmal boundaries of 0 to 9. No carry can be
530
        // generated
531
        if (c[N+1])
532
                o[g*4+3:g*4] = o[g*4+3:g*4] + 4'd5;
533
end
534
        assign co = c[0];
535
end
536
endgenerate
537
 
538
endmodule

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