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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [BCDSubtract.sv] - Blame information for rev 89

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`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      BCDSubtract.sv
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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module BCDSubtract(clk, a, b, o, sgn);
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parameter N=25;
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input clk;
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input [N*4-1:0] a;
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input [N*4-1:0] b;
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output reg [N*4-1:0] o;
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output reg sgn;
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wire [(N)*4-1:0] bc;
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wire [(N)*4-1:0] o1, o2, o3;
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wire c;
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BCDNinesComplementN #(N) u1 (.i({4'h0,b}), .o(bc));
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BCDAddNClk #(.N(N)) u2 (.clk(clk), .a({8'h00,a}), .b(bc), .o(o1), .ci(1'b0), .co(c));
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BCDNinesComplementN #(N) u3 (.i(o1), .o(o2));
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BCDAddNClk #(.N(N)) u4 (.clk(clk), .a(o1), .b('d0), .o(o3), .ci(c), .co());
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always_ff @(posedge clk)
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        if (c)
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                o <= o3;
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        else
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                o <= o2;
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always_ff @(posedge clk)
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        sgn <= |o ? ~c : 1'b0;
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endmodule
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module BCDNinesComplement(i, o);
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input [3:0] i;
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output reg [3:0] o;
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always_comb
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        case(i)
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        4'd0:   o = 4'd9;
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        4'd1:   o = 4'd8;
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        4'd2:   o = 4'd7;
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        4'd3:   o = 4'd6;
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        4'd4: o = 4'd5;
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        4'd5:   o = 4'd4;
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        4'd6:   o = 4'd3;
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        4'd7:   o = 4'd2;
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        4'd8:   o = 4'd1;
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        4'd9:   o = 4'd0;
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        4'd10:  o = 4'd9;
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        4'd11:  o = 4'd8;
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        4'd12:  o = 4'd7;
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        4'd13:  o = 4'd6;
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        4'd14:  o = 4'd5;
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        4'd15:  o = 4'd4;
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        endcase
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endmodule
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module BCDNinesComplementN(i, o);
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parameter N=25;
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input [N*4-1:0] i;
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output [N*4-1:0] o;
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genvar g;
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generate begin : gNC
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        for (g = 0; g < N; g = g + 1)
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                BCDNinesComplement utc1 (i[g*4+3:g*4],o[g*4+3:g*4]);
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end
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endgenerate
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endmodule
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module BCDTensComplement(i, o);
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input [3:0] i;
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output reg [3:0] o;
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always_comb
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        case(i)
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        4'd0:   o = 4'd0;
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        4'd1:   o = 4'd9;
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        4'd2:   o = 4'd8;
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        4'd3:   o = 4'd7;
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        4'd4: o = 4'd6;
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        4'd5:   o = 4'd5;
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        4'd6:   o = 4'd4;
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        4'd7:   o = 4'd3;
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        4'd8:   o = 4'd2;
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        4'd9:   o = 4'd1;
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        4'd10:  o = 4'd0;
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        4'd11:  o = 4'd9;
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        4'd12:  o = 4'd8;
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        4'd13:  o = 4'd7;
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        4'd14:  o = 4'd6;
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        4'd15:  o = 4'd5;
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        endcase
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endmodule
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module BCDTensComplementN(i, o);
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parameter N=25;
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input [N*4-1:0] i;
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output [N*4-1:0] o;
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genvar g;
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generate begin : gTC
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        for (g = 0; g < N; g = g + 1)
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                BCDTensComplement utc1 (i[g*4+3:g*4],o[g*4+3:g*4]);
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end
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endgenerate
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endmodule

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