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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DDBinToBCD.sv] - Blame information for rev 84

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1 59 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      DDBinToBCD.sv
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//  Uses the Dubble Dabble algorithm
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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module DDBinToBCD(rst, clk, ld, bin, bcd, done);
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parameter WID = 128;
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parameter DEP = 2;              // pipeline depth
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localparam BCDWID = ((WID+(WID-4)/3)+3) & -4;
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input rst;
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input clk;
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input ld;
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input [WID-1:0] bin;
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output reg [BCDWID-1:0] bcd;
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output reg done;
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integer k;
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genvar n,g;
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reg [WID-1:0] binw;                                                             // working binary value
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reg [BCDWID-1:0] bcdwt;
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reg [BCDWID-1:0] bcdw [0:DEP-1];        // working bcd value
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reg [7:0] bitcnt;
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reg [2:0] state;
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parameter IDLE = 3'd0;
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parameter CHK5 = 3'd1;
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parameter SHFT = 3'd2;
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parameter DONE = 3'd3;
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function [BCDWID-1:0] fnRow;
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input [BCDWID-1:0] i;
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input lsb;
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begin
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        fnRow = 'd0;
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        for (k = 0; k < BCDWID; k = k + 4)
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                if (((i >> k) & 4'hF) > 4'd4)
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                        fnRow = fnRow | (((i >> k) & 4'hF) + 4'd3) << k;
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                else
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                        fnRow = fnRow | ((i >> k) & 4'hf) << k;
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        fnRow = {fnRow,lsb};
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end
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endfunction
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always_comb
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        bcdw[0] = fnRow(bcdwt,binw[WID-1]);
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generate begin : gRows
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        for (n = 1; n < DEP; n = n + 1)
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                always_comb
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                        bcdw[n] = fnRow(bcdw[n-1],binw[WID-1-n]);
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end
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endgenerate
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always_ff @(posedge clk)
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if (rst) begin
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        state <= IDLE;
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        done <= 1'b1;
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        bcdwt <= 'd0;
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        binw <= 'd0;
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        bitcnt <= 'd0;
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end
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else begin
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        if (ld) begin
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                done <= 1'b0;
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                bitcnt <= (WID+DEP-1)/DEP-1;
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                binw <= bin << DEP;
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                bcdwt <= 'd0;
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                state <= SHFT;
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        end
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        else
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        case(state)
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        IDLE:   ;
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        SHFT:
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                begin
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                        bitcnt <= bitcnt - 2'd1;
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                        if (bitcnt==8'd1) begin
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                                state <= DONE;
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                        end
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                        bcdwt <= bcdw[DEP-1];
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                        binw <= binw << DEP;
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                end
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        DONE:
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                begin
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                        bcd <= bcdwt;
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                        done <= 1'b1;
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                        state <= IDLE;
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                end
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        default:
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                state <= IDLE;
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        endcase
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end
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endmodule

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