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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPAddsub.sv] - Blame information for rev 50

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1 50 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      DFPAddsub.sv
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
37
 
38
module DFPAddsub(clk, ce, rm, op, a, b, o);
39
input clk;
40
input ce;
41
input [2:0] rm;
42
input op;
43
input [127:0] a;
44
input [127:0] b;
45
output [219:0] o;
46
 
47
parameter TRUE = 1'b1;
48
parameter FALSE = 1'b0;
49
 
50
wire sa, sb;
51
wire sxa, sxb;
52
wire adn, bdn;
53
wire xainf, xbinf;
54
wire ainf, binf;
55
wire aNan, bNan;
56
wire [15:0] xa, xb;
57
wire [95:0] siga, sigb;
58
 
59
wire [15:0] xabdif4;
60
BCDSub4 ubcds1(
61
        .ci(1'b0),
62
        .a(xa_gt_xb4 ? xa4 : xb4),
63
        .b(xa_gt_xb4 ? xb4 : xa4),
64
        .o(xabdif4),
65
        .c(),
66
        .c8()
67
);
68
 
69
wire [99:0] oss10;
70
wire oss10c;
71
 
72
BCDAddN #(.N(25)) ubcdan1
73
(
74
        .ci(1'b0),
75
        .a(oaa10),
76
        .b(obb10),
77
        .o(oss10),
78
        .co(oss10c)
79
);
80
 
81
wire [99:0] odd10;
82
wire odd10c;
83
 
84
BCDSubN #(.N(25)) ubcdsn1
85
(
86
        .ci(1'b0),
87
        .a(oaa10),
88
        .b(obb10),
89
        .o(odd10),
90
        .co(odd10c)
91
);
92
 
93
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
94
// Clock #1
95
// - decode the input operands
96
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
97
reg op1;
98
 
99
DFPDecomposeReg u1a (.clk(clk), .ce(ce), .i(a), .sgn(sa), .sx(sxa), .exp(xa), .sig(siga), .xz(adn), .vz(az), .inf(aInf), .nan(aNan) );
100
DFPDecomposeReg u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb), .sx(sxb), .exp(xb), .sig(sigb), .xz(bdn), .vz(bz), .inf(bInf), .nan(bNan) );
101
 
102
always @(posedge clk)
103
  if (ce) op1 <= op;
104
 
105
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
106
// Clock #2
107
//
108
// Figure out which operation is really needed an add or subtract ?
109
// If the signs are the same, use the orignal op,
110
// otherwise flip the operation
111
//  a +  b = add,+
112
//  a + -b = sub, so of larger
113
// -a +  b = sub, so of larger
114
// -a + -b = add,-
115
//  a -  b = sub, so of larger
116
//  a - -b = add,+
117
// -a -  b = add,-
118
// -a - -b = sub, so of larger
119
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
120
reg realOp2;
121
reg op2;
122
reg [15:0] xa2, xb2;
123
reg az2, bz2;
124
reg xa_gt_xb2;
125
reg [95:0] siga2, sigb2;
126
reg sigeq, siga_gt_sigb;
127
reg xa_gt_xb2;
128
reg expeq;
129
reg sxo2;
130
 
131
always @(posedge clk)
132
  if (ce) realOp2 = op1 ^ sa ^ sb;
133
always @(posedge clk)
134
  if (ce) op2 <= op1;
135
always @(posedge clk)
136
  if (ce) xa2 <= xa;
137
always @(posedge clk)
138
  if (ce) xb2 <= xb;
139
always @(posedge clk)
140
  if (ce) siga2 <= siga;
141
always @(posedge clk)
142
  if (ce) sigb2 <= sigb;
143
always @(posedge clk)
144
  if (ce) az2 <= az;
145
always @(posedge clk)
146
  if (ce) bz2 <= bz;
147
always @(posedge clk)
148
  if (ce)
149
        if (sxa & ~sxb)
150
                xa_gt_xb2 <= TRUE;
151
        else if (~sxa & sxb)
152
                xa_gt_xb2 <= FALSE;
153
        else
154
                xa_gt_xb2 <= sxa ? xa > xb : xa < xb;
155
always @(posedge clk)
156
  if (ce)
157
        sxo2 <= sxa|sxb;
158
 
159
always @(posedge clk)
160
  if (ce) sigeq <= siga==sigb;
161
always @(posedge clk)
162
  if (ce) siga_gt_sigb <= siga > sigb;
163
always @(posedge clk)
164
  if (ce) expeq <= {sxa,xa}=={sxb,xb};
165
 
166
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
167
// Clock #3
168
//
169
// Find out if the result will be zero.
170
// Determine which fraction to denormalize
171
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
172
//
173
reg [15:0] xa3, xb3;
174
reg resZero3;
175
wire xaInf3, xbInf3;
176
reg xa_gt_xb3;
177
reg a_gt_b3;
178
reg op3;
179
wire sa3, sb3;
180
wire [2:0] rm3;
181
reg [95:0] mfs3;
182
 
183
always @(posedge clk)
184
  if (ce) resZero3 <= (realOp2 & expeq & sigeq) ||      // subtract, same magnitude
185
                           (az2 & bz2);               // both a,b zero
186
always @(posedge clk)
187
  if (ce) xa3 <= xa2;
188
always @(posedge clk)
189
  if (ce) xb3 <= xb2;
190
always @(posedge clk)
191
  if (ce) xa_gt_xb3 <= xa_gt_xb2;
192
always @(posedge clk)
193
  if (ce) a_gt_b3 <= xa_gt_xb2 | (expeq & siga_gt_sigb);
194
always @(posedge clk)
195
  if (ce) op3 <= op2;
196
always @(posedge clk)
197
  if (ce) mfs3 = xa_gt_xb2 ? sigb2 : siga2;
198
 
199
delay #(.WID(1), .DEP(2)) udly3c (.clk(clk), .ce(ce), .i(sa), .o(sa3));
200
delay #(.WID(1), .DEP(2)) udly3d (.clk(clk), .ce(ce), .i(sb), .o(sb3));
201
delay #(.WID(3), .DEP(3)) udly3e (.clk(clk), .ce(ce), .i(rm), .o(rm3));
202
delay #(.WID(1), .DEP(2)) udly3f (.clk(clk), .ce(ce), .i(aInf), .o(aInf3));
203
delay #(.WID(1), .DEP(2)) udly3g (.clk(clk), .ce(ce), .i(bInf), .o(bInf3));
204
 
205
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
206
// Clock #4
207
//
208
// Compute output exponent
209
//
210
// The output exponent is the larger of the two exponents,
211
// unless a subtract operation is in progress and the two
212
// numbers are equal, in which case the exponent should be
213
// zero.
214
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
215
 
216
reg [15:0] xa4, xb4;
217
reg [15:0] xo4;
218
reg xa_gt_xb4;
219
 
220
always @(posedge clk)
221
  if (ce) xa4 <= xa3;
222
always @(posedge clk)
223
  if (ce) xb4 <= xb3;
224
always @(posedge clk)
225
        if (ce) xo4 <= resZero3 ? 16'd0 : xa_gt_xb3 ? xa3 : xb3;
226
always @(posedge clk)
227
  if (ce) xa_gt_xb4 <= xa_gt_xb3;
228
 
229
// Compute output sign
230
reg so4;
231
always @*
232
        case ({resZero3,sa3,op3,sb3})   // synopsys full_case parallel_case
233
        4'b0000: so4 <= 0;                      // + + + = +
234
        4'b0001: so4 <= !a_gt_b3;       // + + - = sign of larger
235
        4'b0010: so4 <= !a_gt_b3;       // + - + = sign of larger
236
        4'b0011: so4 <= 0;                      // + - - = +
237
        4'b0100: so4 <= a_gt_b3;                // - + + = sign of larger
238
        4'b0101: so4 <= 1;                      // - + - = -
239
        4'b0110: so4 <= 1;                      // - - + = -
240
        4'b0111: so4 <= a_gt_b3;                // - - - = sign of larger
241
        4'b1000: so4 <= 0;                      //  A +  B, sign = +
242
        4'b1001: so4 <= rm3==3'd3;              //  A + -B, sign = + unless rounding down
243
        4'b1010: so4 <= rm3==3'd3;              //  A -  B, sign = + unless rounding down
244
        4'b1011: so4 <= 0;                      // +A - -B, sign = +
245
        4'b1100: so4 <= rm3==3'd3;              // -A +  B, sign = + unless rounding down
246
        4'b1101: so4 <= 1;                      // -A + -B, sign = -
247
        4'b1110: so4 <= 1;                      // -A - +B, sign = -
248
        4'b1111: so4 <= rm3==3'd3;              // -A - -B, sign = + unless rounding down
249
        endcase
250
 
251
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
252
// Clock #5
253
//
254
// Compute the difference in exponents, provides shift amount
255
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
256
reg [15:0] xdiff5;
257
always @(posedge clk)
258
  if (ce) xdiff5 <= xabdif4;
259
 
260
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
261
// Clock #6
262
//
263
// Compute the difference in exponents, provides shift amount
264
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
265
// If the difference in the exponent is 24 or greater (assuming 24 nybble dfp or
266
// less) then all of the bits will be shifted out to zero. There is no need to
267
// keep track of a difference more than 24.
268
reg [11:0] xdif6;
269
wire [95:0] mfs6;
270
always @(posedge clk)
271
  if (ce) xdif6 <= xdiff5 > 16'h0024 ? 8'h24 : xdiff5[7:0];
272
delay #(.WID(96), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6));
273
 
274
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
275
// Clock #7
276
//
277
// Determine the sticky bit. The sticky bit is the bitwise or of all the bits
278
// being shifted out the right side. The sticky bit is computed here to
279
// reduce the number of regs required.
280
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
281
reg sticky6;
282
wire sticky7;
283
wire [7:0] xdif7;
284
wire [95:0] mfs7;
285
wire [7:0] xdif6a = {xdif6[7:4] * 10 + xdif6[3:0],2'b00};       // Convert base then *4
286
integer n;
287
always @* begin
288
        sticky6 = 1'b0;
289
        for (n = 0; n < 96; n = n + 4)
290
                if (n <= xdif6a)
291
                        sticky6 = sticky6| mfs6[n]|mfs6[n+1]|mfs6[n+2]|mfs6[n+3];       // non-zeero nybble
292
end
293
 
294
// register inputs to shifter and shift
295
delay1 #(1)  d16(.clk(clk), .ce(ce), .i(sticky6), .o(sticky7) );
296
delay1 #(8)  d15(.clk(clk), .ce(ce), .i(xdif6a),   .o(xdif7) );
297
delay1 #(96) d14(.clk(clk), .ce(ce), .i(mfs6),    .o(mfs7) );
298
 
299
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
300
// Clock #8
301
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
302
reg [99:0] md8;
303
wire [95:0] siga8, sigb8;
304
wire xa_gt_xb8;
305
wire a_gt_b8;
306
always @(posedge clk)
307
  if (ce) md8 <= ({mfs7,4'b0} >> xdif7)|sticky7; // xdif7 is a multiple of four
308
 
309
// sync control signals
310
delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8));
311
delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8));
312
delay #(.WID(96), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8));
313
delay #(.WID(96), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8));
314
delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8));
315
 
316
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
317
// Clock #9
318
// Sort operands and perform add/subtract
319
// addition can generate an extra bit, subtract can't go negative
320
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
321
reg [99:0] oa9, ob9;
322
reg a_gt_b9;
323
always @(posedge clk)
324
  if (ce) oa9 <= xa_gt_xb8 ? {siga8,4'b0} : md8;
325
always @(posedge clk)
326
  if (ce) ob9 <= xa_gt_xb8 ? md8 : {sigb8,4'b0};
327
always @(posedge clk)
328
  if (ce) a_gt_b9 <= a_gt_b8;
329
 
330
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
331
// Clock #10
332
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
333
reg [99:0] oaa10;
334
reg [99:0] obb10;
335
wire realOp10;
336
reg [15:0] xo10;
337
 
338
always @(posedge clk)
339
  if (ce) oaa10 <= a_gt_b9 ? oa9 : ob9;
340
always @(posedge clk)
341
  if (ce) obb10 <= a_gt_b9 ? ob9 : oa9;
342
delay #(.WID(1), .DEP(8)) udly10a (.clk(clk), .ce(ce), .i(realOp2), .o(realOp10));
343
delay #(.WID(16), .DEP(6)) udly10b (.clk(clk), .ce(ce), .i(xo4), .o(xo10));
344
 
345
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
346
// Clock #11
347
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
348
reg [99:0] mab11;
349
reg mab11c;
350
wire [95:0] siga11, sigb11;
351
wire abInf11;
352
wire aNan11, bNan11;
353
reg xoinf11;
354
wire op11;
355
 
356
always @(posedge clk)
357
  if (ce) mab11 <= realOp10 ? odd10 : oss10;
358
always @(posedge clk)
359
        if (ce) mab11c <= realOp10 ? odd10c : oss10c;
360
 
361
delay #(.WID(1), .DEP(8)) udly11a (.clk(clk), .ce(ce), .i(aInf3&bInf3), .o(abInf11));
362
delay #(.WID(1), .DEP(10)) udly11c (.clk(clk), .ce(ce), .i(aNan), .o(aNan11));
363
delay #(.WID(1), .DEP(10)) udly11d (.clk(clk), .ce(ce), .i(bNan), .o(bNan11));
364
delay #(.WID(1), .DEP(3)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11));
365
delay #(.WID(96), .DEP(3)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11));
366
delay #(.WID(96), .DEP(3)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11));
367
 
368
always @(posedge clk)
369
  if (ce) xoinf11 <= xo10==16'h9999;
370
 
371
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
372
// Clock #12
373
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
374
reg [199:0] mo12;       // mantissa output
375
reg [3:0] st12;
376
wire sxo11;
377
wire so11;
378
delay #(.WID(1), .DEP(9)) udly12a (.clk(clk), .ce(ce), .i(sxo2), .o(sxo11));
379
delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
380
 
381
always @(posedge clk)
382
if (ce) begin
383
        st12[0] <= sxo11;
384
        st12[1] <= abInf11;
385
        st12[2] <= so11;
386
        st12[3] <= aNan11|bNan11;
387
end
388
 
389
always @(posedge clk)
390
if (ce)
391
        casez({abInf11,aNan11,bNan11,xoinf11})
392
        4'b1???:        // inf +/- inf - generate QNaN on subtract, inf on add
393
                if (op11)
394
                        mo12 <= {4'h9,196'd0};
395
                else
396
                        mo12 <= {50{4'h9}};
397
        4'b01??:        mo12 <= {4'b0,siga11[95:0],100'd0};
398
        4'b001?:        mo12 <= {4'b0,sigb11[95:0],100'd0};
399
        4'b0001:        mo12 <= 200'd0;
400
        default:        mo12 <= {3'b0,mab11c,mab11,96'd0};      // mab has an extra lead bit and four trailing bits
401
        endcase
402
 
403
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
404
// Clock #13
405
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
406
wire so;                        // sign output
407
wire [3:0] st;
408
wire [15:0] xo; // de normalized exponent output
409
wire [199:0] mo;        // mantissa output
410
 
411
delay #(.WID(4), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(st12), .o(st[3:0]) );
412
delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(so));
413
delay #(.WID(16), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(xo));
414
delay #(.WID(200), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(mo12), .o(mo) );
415
 
416
assign o = {st,xo,mo};
417
 
418
endmodule
419
 
420
 
421
module DFPAddsubnr(clk, ce, rm, op, a, b, o);
422
input clk;              // system clock
423
input ce;               // core clock enable
424
input [2:0] rm; // rounding mode
425
input op;               // operation 0 = add, 1 = subtract
426
input [127:0] a;        // operand a
427
input [127:0] b;        // operand b
428
output [127:0] o;       // output
429
 
430
wire [219:0] o1;
431
wire [119:0] fpn0;
432
 
433
DFPAddsub    u1 (clk, ce, rm, op, a, b, o1);
434
DFPNormalize u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
435
DFPRound        u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
436
 
437
endmodule

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