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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPAddsub.sv] - Blame information for rev 84

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1 50 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      DFPAddsub.sv
9
//
10
// BSD 3-Clause License
11
// Redistribution and use in source and binary forms, with or without
12
// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
15
//    list of conditions and the following disclaimer.
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//
17
// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
21
// 3. Neither the name of the copyright holder nor the names of its
22
//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35
//
36
// ============================================================================
37
 
38
module DFPAddsub(clk, ce, rm, op, a, b, o);
39 55 robfinch
parameter N=33;
40 50 robfinch
input clk;
41
input ce;
42
input [2:0] rm;
43
input op;
44 55 robfinch
input [N*4+16+4-1:0] a;
45
input [N*4+16+4-1:0] b;
46
output [(N+1)*4*2+16+4-1:0] o;
47 50 robfinch
 
48
parameter TRUE = 1'b1;
49
parameter FALSE = 1'b0;
50
 
51
wire sa, sb;
52
wire sxa, sxb;
53
wire adn, bdn;
54
wire xainf, xbinf;
55
wire ainf, binf;
56
wire aNan, bNan;
57
wire [15:0] xa, xb;
58 55 robfinch
wire [N*4-1:0] siga, sigb;
59 50 robfinch
 
60
wire [15:0] xabdif4;
61
BCDSub4 ubcds1(
62
        .ci(1'b0),
63
        .a(xa_gt_xb4 ? xa4 : xb4),
64
        .b(xa_gt_xb4 ? xb4 : xa4),
65
        .o(xabdif4),
66
        .c(),
67
        .c8()
68
);
69
 
70 55 robfinch
wire [(N+1)*4-1:0] oss10;
71 50 robfinch
wire oss10c;
72
 
73 55 robfinch
BCDAddN #(.N(N+1)) ubcdan1
74 50 robfinch
(
75
        .ci(1'b0),
76
        .a(oaa10),
77
        .b(obb10),
78
        .o(oss10),
79
        .co(oss10c)
80
);
81
 
82 55 robfinch
wire [(N+1)*4-1:0] odd10;
83 50 robfinch
wire odd10c;
84
 
85 55 robfinch
BCDSubN #(.N(N+1)) ubcdsn1
86 50 robfinch
(
87
        .ci(1'b0),
88
        .a(oaa10),
89
        .b(obb10),
90
        .o(odd10),
91
        .co(odd10c)
92
);
93
 
94
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
95
// Clock #1
96
// - decode the input operands
97
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
98
reg op1;
99
 
100 55 robfinch
DFPDecomposeReg #(.N(N)) u1a (.clk(clk), .ce(ce), .i(a), .sgn(sa), .sx(sxa), .exp(xa), .sig(siga), .xz(adn), .vz(az), .inf(aInf), .nan(aNan) );
101
DFPDecomposeReg #(.N(N)) u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb), .sx(sxb), .exp(xb), .sig(sigb), .xz(bdn), .vz(bz), .inf(bInf), .nan(bNan) );
102 50 robfinch
 
103
always @(posedge clk)
104
  if (ce) op1 <= op;
105
 
106
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
107
// Clock #2
108
//
109
// Figure out which operation is really needed an add or subtract ?
110
// If the signs are the same, use the orignal op,
111
// otherwise flip the operation
112
//  a +  b = add,+
113
//  a + -b = sub, so of larger
114
// -a +  b = sub, so of larger
115
// -a + -b = add,-
116
//  a -  b = sub, so of larger
117
//  a - -b = add,+
118
// -a -  b = add,-
119
// -a - -b = sub, so of larger
120
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
121
reg realOp2;
122
reg op2;
123
reg [15:0] xa2, xb2;
124
reg az2, bz2;
125
reg xa_gt_xb2;
126 55 robfinch
reg [N*4-1:0] siga2, sigb2;
127 50 robfinch
reg sigeq, siga_gt_sigb;
128
reg xa_gt_xb2;
129
reg expeq;
130
reg sxo2;
131
 
132
always @(posedge clk)
133
  if (ce) realOp2 = op1 ^ sa ^ sb;
134
always @(posedge clk)
135
  if (ce) op2 <= op1;
136
always @(posedge clk)
137
  if (ce) xa2 <= xa;
138
always @(posedge clk)
139
  if (ce) xb2 <= xb;
140
always @(posedge clk)
141
  if (ce) siga2 <= siga;
142
always @(posedge clk)
143
  if (ce) sigb2 <= sigb;
144
always @(posedge clk)
145
  if (ce) az2 <= az;
146
always @(posedge clk)
147
  if (ce) bz2 <= bz;
148
always @(posedge clk)
149
  if (ce)
150
        if (sxa & ~sxb)
151
                xa_gt_xb2 <= TRUE;
152
        else if (~sxa & sxb)
153
                xa_gt_xb2 <= FALSE;
154
        else
155
                xa_gt_xb2 <= sxa ? xa > xb : xa < xb;
156
always @(posedge clk)
157
  if (ce)
158
        sxo2 <= sxa|sxb;
159
 
160
always @(posedge clk)
161
  if (ce) sigeq <= siga==sigb;
162
always @(posedge clk)
163
  if (ce) siga_gt_sigb <= siga > sigb;
164
always @(posedge clk)
165
  if (ce) expeq <= {sxa,xa}=={sxb,xb};
166
 
167
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
168
// Clock #3
169
//
170
// Find out if the result will be zero.
171
// Determine which fraction to denormalize
172
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
173
//
174
reg [15:0] xa3, xb3;
175
reg resZero3;
176
wire xaInf3, xbInf3;
177
reg xa_gt_xb3;
178
reg a_gt_b3;
179
reg op3;
180
wire sa3, sb3;
181
wire [2:0] rm3;
182 55 robfinch
reg [N*4-1:0] mfs3;
183 50 robfinch
 
184
always @(posedge clk)
185
  if (ce) resZero3 <= (realOp2 & expeq & sigeq) ||      // subtract, same magnitude
186
                           (az2 & bz2);               // both a,b zero
187
always @(posedge clk)
188
  if (ce) xa3 <= xa2;
189
always @(posedge clk)
190
  if (ce) xb3 <= xb2;
191
always @(posedge clk)
192
  if (ce) xa_gt_xb3 <= xa_gt_xb2;
193
always @(posedge clk)
194
  if (ce) a_gt_b3 <= xa_gt_xb2 | (expeq & siga_gt_sigb);
195
always @(posedge clk)
196
  if (ce) op3 <= op2;
197
always @(posedge clk)
198
  if (ce) mfs3 = xa_gt_xb2 ? sigb2 : siga2;
199
 
200
delay #(.WID(1), .DEP(2)) udly3c (.clk(clk), .ce(ce), .i(sa), .o(sa3));
201
delay #(.WID(1), .DEP(2)) udly3d (.clk(clk), .ce(ce), .i(sb), .o(sb3));
202
delay #(.WID(3), .DEP(3)) udly3e (.clk(clk), .ce(ce), .i(rm), .o(rm3));
203
delay #(.WID(1), .DEP(2)) udly3f (.clk(clk), .ce(ce), .i(aInf), .o(aInf3));
204
delay #(.WID(1), .DEP(2)) udly3g (.clk(clk), .ce(ce), .i(bInf), .o(bInf3));
205
 
206
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
207
// Clock #4
208
//
209
// Compute output exponent
210
//
211
// The output exponent is the larger of the two exponents,
212
// unless a subtract operation is in progress and the two
213
// numbers are equal, in which case the exponent should be
214
// zero.
215
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
216
 
217
reg [15:0] xa4, xb4;
218
reg [15:0] xo4;
219
reg xa_gt_xb4;
220
 
221
always @(posedge clk)
222
  if (ce) xa4 <= xa3;
223
always @(posedge clk)
224
  if (ce) xb4 <= xb3;
225
always @(posedge clk)
226
        if (ce) xo4 <= resZero3 ? 16'd0 : xa_gt_xb3 ? xa3 : xb3;
227
always @(posedge clk)
228
  if (ce) xa_gt_xb4 <= xa_gt_xb3;
229
 
230
// Compute output sign
231
reg so4;
232
always @*
233
        case ({resZero3,sa3,op3,sb3})   // synopsys full_case parallel_case
234 55 robfinch
        4'b0000: so4 <= 0;                      // - + - = -
235
        4'b0001: so4 <= !a_gt_b3;       // - + + = sign of larger
236
        4'b0010: so4 <= !a_gt_b3;       // - - - = sign of larger
237
        4'b0011: so4 <= 0;                      // - - + = -
238
        4'b0100: so4 <= a_gt_b3;                // + + - = sign of larger
239
        4'b0101: so4 <= 1;                      // + + + = +
240
        4'b0110: so4 <= 1;                      // + - - = +
241
        4'b0111: so4 <= a_gt_b3;                // + - + = sign of larger
242
        4'b1000: so4 <= 0;                      //  -A +  -B, sign = -
243
        4'b1001: so4 <= (rm3==3'd3);            //  -A + B, sign = + unless rounding down
244
        4'b1010: so4 <= (rm3==3'd3);            //  -A - -B, sign = + unless rounding down
245
        4'b1011: so4 <= 0;                      // -A - B, sign = -
246
        4'b1100: so4 <= (rm3==3'd3);            // A -  B, sign = + unless rounding down
247
        4'b1101: so4 <= 1;                      // A + B, sign = +
248
        4'b1110: so4 <= 1;                      // A - -B, sign = +
249
        4'b1111: so4 <= (rm3==3'd3);            // -A - -B, sign = + unless rounding down
250 50 robfinch
        endcase
251
 
252
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
253
// Clock #5
254
//
255
// Compute the difference in exponents, provides shift amount
256
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
257
reg [15:0] xdiff5;
258
always @(posedge clk)
259
  if (ce) xdiff5 <= xabdif4;
260
 
261
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
262
// Clock #6
263
//
264
// Compute the difference in exponents, provides shift amount
265
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
266
// If the difference in the exponent is 24 or greater (assuming 24 nybble dfp or
267
// less) then all of the bits will be shifted out to zero. There is no need to
268
// keep track of a difference more than 24.
269
reg [11:0] xdif6;
270 55 robfinch
wire [N*4-1:0] mfs6;
271 50 robfinch
always @(posedge clk)
272 55 robfinch
  if (ce) xdif6 <= xdiff5 > N ? N : xdiff5[7:0];
273
delay #(.WID(N*4), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6));
274 50 robfinch
 
275
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
276
// Clock #7
277
//
278
// Determine the sticky bit. The sticky bit is the bitwise or of all the bits
279
// being shifted out the right side. The sticky bit is computed here to
280
// reduce the number of regs required.
281
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
282
reg sticky6;
283
wire sticky7;
284
wire [7:0] xdif7;
285 55 robfinch
wire [N*4-1:0] mfs7;
286 50 robfinch
wire [7:0] xdif6a = {xdif6[7:4] * 10 + xdif6[3:0],2'b00};       // Convert base then *4
287
integer n;
288
always @* begin
289
        sticky6 = 1'b0;
290 55 robfinch
        for (n = 0; n < N*4; n = n + 4)
291 50 robfinch
                if (n <= xdif6a)
292
                        sticky6 = sticky6| mfs6[n]|mfs6[n+1]|mfs6[n+2]|mfs6[n+3];       // non-zeero nybble
293
end
294
 
295
// register inputs to shifter and shift
296
delay1 #(1)  d16(.clk(clk), .ce(ce), .i(sticky6), .o(sticky7) );
297
delay1 #(8)  d15(.clk(clk), .ce(ce), .i(xdif6a),   .o(xdif7) );
298 55 robfinch
delay1 #(N*4) d14(.clk(clk), .ce(ce), .i(mfs6),    .o(mfs7) );
299 50 robfinch
 
300
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
301
// Clock #8
302
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
303 55 robfinch
reg [(N+1)*4-1:0] md8;
304
wire [N*4-1:0] siga8, sigb8;
305 50 robfinch
wire xa_gt_xb8;
306
wire a_gt_b8;
307
always @(posedge clk)
308
  if (ce) md8 <= ({mfs7,4'b0} >> xdif7)|sticky7; // xdif7 is a multiple of four
309
 
310
// sync control signals
311
delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8));
312
delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8));
313 55 robfinch
delay #(.WID(N*4), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8));
314
delay #(.WID(N*4), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8));
315 50 robfinch
delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8));
316
 
317
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
318
// Clock #9
319
// Sort operands and perform add/subtract
320
// addition can generate an extra bit, subtract can't go negative
321
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
322 55 robfinch
reg [(N+1)*4-1:0] oa9, ob9;
323 50 robfinch
reg a_gt_b9;
324
always @(posedge clk)
325
  if (ce) oa9 <= xa_gt_xb8 ? {siga8,4'b0} : md8;
326
always @(posedge clk)
327
  if (ce) ob9 <= xa_gt_xb8 ? md8 : {sigb8,4'b0};
328
always @(posedge clk)
329
  if (ce) a_gt_b9 <= a_gt_b8;
330
 
331
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
332
// Clock #10
333
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
334 55 robfinch
reg [(N+1)*4-1:0] oaa10;
335
reg [(N+1)*4-1:0] obb10;
336 50 robfinch
wire realOp10;
337
reg [15:0] xo10;
338
 
339
always @(posedge clk)
340
  if (ce) oaa10 <= a_gt_b9 ? oa9 : ob9;
341
always @(posedge clk)
342
  if (ce) obb10 <= a_gt_b9 ? ob9 : oa9;
343
delay #(.WID(1), .DEP(8)) udly10a (.clk(clk), .ce(ce), .i(realOp2), .o(realOp10));
344
delay #(.WID(16), .DEP(6)) udly10b (.clk(clk), .ce(ce), .i(xo4), .o(xo10));
345
 
346
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
347
// Clock #11
348
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
349 55 robfinch
reg [(N+1)*4-1:0] mab11;
350 50 robfinch
reg mab11c;
351 55 robfinch
wire [N*4-1:0] siga11, sigb11;
352 50 robfinch
wire abInf11;
353
wire aNan11, bNan11;
354
reg xoinf11;
355
wire op11;
356
 
357
always @(posedge clk)
358
  if (ce) mab11 <= realOp10 ? odd10 : oss10;
359
always @(posedge clk)
360
        if (ce) mab11c <= realOp10 ? odd10c : oss10c;
361
 
362
delay #(.WID(1), .DEP(8)) udly11a (.clk(clk), .ce(ce), .i(aInf3&bInf3), .o(abInf11));
363
delay #(.WID(1), .DEP(10)) udly11c (.clk(clk), .ce(ce), .i(aNan), .o(aNan11));
364
delay #(.WID(1), .DEP(10)) udly11d (.clk(clk), .ce(ce), .i(bNan), .o(bNan11));
365
delay #(.WID(1), .DEP(3)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11));
366 55 robfinch
delay #(.WID(N*4), .DEP(3)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11));
367
delay #(.WID(N*4), .DEP(3)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11));
368 50 robfinch
 
369
always @(posedge clk)
370
  if (ce) xoinf11 <= xo10==16'h9999;
371
 
372
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
373
// Clock #12
374
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
375 55 robfinch
reg [(N+1)*4*2-1:0] mo12;       // mantissa output
376 50 robfinch
reg [3:0] st12;
377
wire sxo11;
378
wire so11;
379
delay #(.WID(1), .DEP(9)) udly12a (.clk(clk), .ce(ce), .i(sxo2), .o(sxo11));
380
delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
381
 
382
always @(posedge clk)
383
if (ce) begin
384
        st12[0] <= sxo11;
385
        st12[1] <= abInf11;
386
        st12[2] <= so11;
387
        st12[3] <= aNan11|bNan11;
388
end
389
 
390
always @(posedge clk)
391
if (ce)
392
        casez({abInf11,aNan11,bNan11,xoinf11})
393
        4'b1???:        // inf +/- inf - generate QNaN on subtract, inf on add
394
                if (op11)
395 55 robfinch
                        mo12 <= {4'h9,{(N+1)*4*2-4{1'd0}}};
396 50 robfinch
                else
397 55 robfinch
                        mo12 <= {(N+1)*2{4'h9}};
398
        4'b01??:        mo12 <= {4'b0,siga11[107:0],{(N+1)*4{1'd0}}};
399
        4'b001?:        mo12 <= {4'b0,sigb11[107:0],{(N+1)*4{1'd0}}};
400
        4'b0001:        mo12 <= {(N+1)*4*2{1'd0}};
401
        default:        mo12 <= {3'b0,mab11c,mab11,{N*4{1'd0}}};        // mab has an extra lead bit and four trailing bits
402 50 robfinch
        endcase
403
 
404
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
405
// Clock #13
406
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
407
wire so;                        // sign output
408
wire [3:0] st;
409
wire [15:0] xo; // de normalized exponent output
410 55 robfinch
wire [(N+1)*4*2-1:0] mo;        // mantissa output
411 50 robfinch
 
412
delay #(.WID(4), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(st12), .o(st[3:0]) );
413
delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(so));
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delay #(.WID(16), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(xo));
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delay #(.WID((N+1)*4*2), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(mo12), .o(mo) );
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assign o = {st,xo,mo};
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endmodule
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module DFPAddsubnr(clk, ce, rm, op, a, b, o);
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parameter N=33;
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input clk;              // system clock
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input ce;               // core clock enable
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input [2:0] rm; // rounding mode
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input op;               // operation 0 = add, 1 = subtract
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input [N*4+16+4-1:0] a; // operand a
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input [N*4+16+4-1:0] b; // operand b
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output [N*4+16+4-1:0] o;        // output
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wire [(N+1)*4*2+16+4-1:0] o1;
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wire [N*4+16+4-1+4:0] fpn0;
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DFPAddsub    u1 (clk, ce, rm, op, a, b, o1);
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DFPNormalize u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
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DFPRound        u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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endmodule

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