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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPAddsub128.sv] - Blame information for rev 84

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      DFPAddsub.sv
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
37
 
38
import DFPPkg::*;
39
 
40
module DFPAddsub128(clk, ce, rm, op, a, b, o);
41
input clk;
42
input ce;
43
input [2:0] rm;
44
input op;
45
input DFP128 a;
46
input DFP128 b;
47
output DFP128UD o;
48
localparam N=34;                        // number of BCD digits
49 64 robfinch
localparam RIP_STAGES = 3;
50 57 robfinch
 
51
parameter TRUE = 1'b1;
52
parameter FALSE = 1'b0;
53
 
54
DFP128U au;
55
DFP128U bu;
56
 
57
DFPUnpack128 u00 (a, au);
58
DFPUnpack128 u01 (b, bu);
59
 
60 64 robfinch
reg [(N+1)*4-1:0] oaa10;
61
reg [(N+1)*4-1:0] obb10;
62 57 robfinch
wire [(N+1)*4-1:0] oss10;
63
wire oss10c;
64
 
65 64 robfinch
BCDAdd8NClk #(.N((N+2)/2)) ubcdadn1
66 57 robfinch
(
67 64 robfinch
        .clk(clk),
68
        .a({8'h00,oaa10}),
69
        .b({8'h00,obb10}),
70
        .o(oss10),
71 57 robfinch
        .ci(1'b0),
72
        .co(oss10c)
73
);
74
 
75
wire [(N+1)*4-1:0] odd10;
76
wire odd10c;
77
 
78 64 robfinch
BCDSub8NClk #(.N((N+2)/2)) ubcdsdn1
79 57 robfinch
(
80 64 robfinch
        .clk(clk),
81
        .a({8'h00,oaa10}),
82
        .b({8'h00,obb10}),
83
        .o(odd10),
84 57 robfinch
        .ci(1'b0),
85
        .co(odd10c)
86
);
87
 
88
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
89
// Clock #1
90
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
91
reg op1;
92
reg az, bz;
93 64 robfinch
always_ff @(posedge clk)
94 57 robfinch
        op1 <= op;
95 64 robfinch
always_ff @(posedge clk)
96 57 robfinch
        az <= au.sig==136'd0 && au.exp==14'd0;
97 64 robfinch
always_ff @(posedge clk)
98 57 robfinch
        bz <= bu.sig==136'd0 && bu.exp==14'd0;
99
 
100
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
101
// Clock #2
102
//
103
// Figure out which operation is really needed an add or subtract ?
104
// If the signs are the same, use the orignal op,
105
// otherwise flip the operation
106
//  a +  b = add,+
107
//  a + -b = sub, so of larger
108
// -a +  b = sub, so of larger
109
// -a + -b = add,-
110
//  a -  b = sub, so of larger
111
//  a - -b = add,+
112
// -a -  b = add,-
113
// -a - -b = sub, so of larger
114
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
115
reg realOp2;
116
reg op2;
117
reg [15:0] xa2, xb2;
118
reg az2, bz2;
119
reg xa_gt_xb2;
120
reg [N*4-1:0] siga2, sigb2;
121
reg sigeq, siga_gt_sigb;
122
reg expeq;
123
reg sxo2;
124
 
125 64 robfinch
always_ff @(posedge clk)
126 57 robfinch
  if (ce) realOp2 = op1 ^ au.sign ^ bu.sign;
127 64 robfinch
always_ff @(posedge clk)
128 57 robfinch
  if (ce) op2 <= op1;
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always_ff @(posedge clk)
130 57 robfinch
  if (ce) xa2 <= au.exp;
131 64 robfinch
always_ff @(posedge clk)
132 57 robfinch
  if (ce) xb2 <= bu.exp;
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always_ff @(posedge clk)
134 57 robfinch
  if (ce) siga2 <= au.sig;
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always_ff @(posedge clk)
136 57 robfinch
  if (ce) sigb2 <= bu.sig;
137 64 robfinch
always_ff @(posedge clk)
138 57 robfinch
  if (ce) az2 <= az;
139 64 robfinch
always_ff @(posedge clk)
140 57 robfinch
  if (ce) bz2 <= bz;
141 64 robfinch
always_ff @(posedge clk)
142 57 robfinch
  if (ce)
143
        xa_gt_xb2 <= au.exp > bu.exp;
144
 
145 64 robfinch
always_ff @(posedge clk)
146 57 robfinch
  if (ce) sigeq <= au.sig==bu.sig;
147 64 robfinch
always_ff @(posedge clk)
148 57 robfinch
  if (ce) siga_gt_sigb <= au.sig > bu.sig;
149 64 robfinch
always_ff @(posedge clk)
150 57 robfinch
  if (ce) expeq <= au.exp==bu.exp;
151
 
152
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
153
// Clock #3
154
//
155
// Find out if the result will be zero.
156
// Determine which fraction to denormalize
157
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
158
//
159
reg [13:0] xa3, xb3;
160
reg resZero3;
161
wire xaInf3, xbInf3;
162
reg xa_gt_xb3;
163
reg a_gt_b3;
164
reg op3;
165
wire sa3, sb3;
166
wire [2:0] rm3;
167
reg [N*4-1:0] mfs3;
168
 
169 64 robfinch
always_ff @(posedge clk)
170 57 robfinch
  if (ce) resZero3 <= (realOp2 & expeq & sigeq) ||      // subtract, same magnitude
171
                           (az2 & bz2);               // both a,b zero
172 64 robfinch
always_ff @(posedge clk)
173 57 robfinch
  if (ce) xa3 <= xa2;
174 64 robfinch
always_ff @(posedge clk)
175 57 robfinch
  if (ce) xb3 <= xb2;
176 64 robfinch
always_ff @(posedge clk)
177 57 robfinch
  if (ce) xa_gt_xb3 <= xa_gt_xb2;
178 64 robfinch
always_ff @(posedge clk)
179 57 robfinch
  if (ce) a_gt_b3 <= xa_gt_xb2 | (expeq & siga_gt_sigb);
180 64 robfinch
always_ff @(posedge clk)
181 57 robfinch
  if (ce) op3 <= op2;
182 64 robfinch
always_ff @(posedge clk)
183 57 robfinch
  if (ce) mfs3 = xa_gt_xb2 ? sigb2 : siga2;
184
 
185 64 robfinch
ft_delay #(.WID(1), .DEP(2)) udly3c (.clk(clk), .ce(ce), .i(au.sign), .o(sa3));
186
ft_delay #(.WID(1), .DEP(2)) udly3d (.clk(clk), .ce(ce), .i(bu.sign), .o(sb3));
187
ft_delay #(.WID(3), .DEP(3)) udly3e (.clk(clk), .ce(ce), .i(rm), .o(rm3));
188
ft_delay #(.WID(1), .DEP(2)) udly3f (.clk(clk), .ce(ce), .i(aInf), .o(aInf3));
189
ft_delay #(.WID(1), .DEP(2)) udly3g (.clk(clk), .ce(ce), .i(bInf), .o(bInf3));
190 57 robfinch
 
191
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
192
// Clock #4
193
//
194
// Compute output exponent
195
//
196
// The output exponent is the larger of the two exponents,
197
// unless a subtract operation is in progress and the two
198
// numbers are equal, in which case the exponent should be
199
// zero.
200
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
201
 
202
reg [13:0] xa4, xb4;
203
reg [13:0] xo4;
204
reg xa_gt_xb4;
205
 
206 64 robfinch
always_ff @(posedge clk)
207 57 robfinch
  if (ce) xa4 <= xa3;
208 64 robfinch
always_ff @(posedge clk)
209 57 robfinch
  if (ce) xb4 <= xb3;
210 64 robfinch
always_ff @(posedge clk)
211 57 robfinch
        if (ce) xo4 <= resZero3 ? 14'd0 : xa_gt_xb3 ? xa3 : xb3;
212 64 robfinch
always_ff @(posedge clk)
213 57 robfinch
  if (ce) xa_gt_xb4 <= xa_gt_xb3;
214
 
215
// Compute output sign
216
reg so4;
217 64 robfinch
always_comb
218 57 robfinch
        case ({resZero3,sa3,op3,sb3})   // synopsys full_case parallel_case
219
        4'b0000: so4 <= 0;                      // + + + = +
220
        4'b0001: so4 <= !a_gt_b3;       // + + - = sign of larger
221
        4'b0010: so4 <= !a_gt_b3;       // + - + = sign of larger
222
        4'b0011: so4 <= 0;                      // + - - = +
223
        4'b0100: so4 <= a_gt_b3;                // - + + = sign of larger
224
        4'b0101: so4 <= 1;                      // - + - = -
225
        4'b0110: so4 <= 1;                      // - - + = -
226
        4'b0111: so4 <= a_gt_b3;                // - - - = sign of larger
227
        4'b1000: so4 <= 0;                      //  A +  B, sign = +
228
        4'b1001: so4 <= (rm3==3'd3);            //  A + -B, sign = + unless rounding down
229
        4'b1010: so4 <= (rm3==3'd3);            //  A - B, sign = + unless rounding down
230
        4'b1011: so4 <= 0;                      // A - -B, sign = +
231
        4'b1100: so4 <= (rm3==3'd3);            // -A -  -B, sign = + unless rounding down
232
        4'b1101: so4 <= 1;                      // -A + -B, sign = -
233
        4'b1110: so4 <= 1;                      // -A - +B, sign = -
234
        4'b1111: so4 <= (rm3==3'd3);            // A - B, sign = + unless rounding down
235
        endcase
236
 
237
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
238
// Clock #5
239
//
240
// Compute the difference in exponents, provides shift amount
241
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
242
reg [13:0] xdiff5;
243 64 robfinch
always_ff @(posedge clk)
244 57 robfinch
  if (ce) xdiff5 <= xa_gt_xb4 ? xa4 - xb4 : xb4 - xa4;
245
 
246
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
247
// Clock #6
248
//
249
// Compute the difference in exponents, provides shift amount
250
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
251
// If the difference in the exponent is 24 or greater (assuming 24 nybble dfp or
252
// less) then all of the bits will be shifted out to zero. There is no need to
253
// keep track of a difference more than 24.
254
reg [6:0] xdif6;
255
wire [N*4-1:0] mfs6;
256 64 robfinch
always_ff @(posedge clk)
257 57 robfinch
  if (ce) xdif6 <= xdiff5 > N ? N : xdiff5[6:0];
258 64 robfinch
ft_delay #(.WID(N*4), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6));
259 57 robfinch
 
260
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
261
// Clock #7
262
//
263
// Determine the sticky bit. The sticky bit is the bitwise or of all the bits
264
// being shifted out the right side. The sticky bit is computed here to
265
// reduce the number of regs required.
266
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
267
reg sticky6;
268
wire sticky7;
269
wire [7:0] xdif7;
270
wire [N*4-1:0] mfs7;
271
wire [8:0] xdif6a = {xdif6,2'b00};      // *4
272
integer n;
273 64 robfinch
always @*
274
begin
275 57 robfinch
        sticky6 = 1'b0;
276
        for (n = 0; n < N*4; n = n + 4)
277
                if (n <= xdif6a)
278
                        sticky6 = sticky6| mfs6[n]|mfs6[n+1]|mfs6[n+2]|mfs6[n+3];       // non-zero nybble
279
end
280
 
281
// register inputs to shifter and shift
282
delay1 #(1)  d16(.clk(clk), .ce(ce), .i(sticky6), .o(sticky7) );
283
delay1 #(9)  d15(.clk(clk), .ce(ce), .i(xdif6a),   .o(xdif7) );
284
delay1 #(N*4) d14(.clk(clk), .ce(ce), .i(mfs6),    .o(mfs7) );
285
 
286
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
287
// Clock #8
288
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
289
reg [(N+1)*4-1:0] md8;
290
wire [N*4-1:0] siga8, sigb8;
291
wire xa_gt_xb8;
292
wire a_gt_b8;
293 64 robfinch
always_ff @(posedge clk)
294 57 robfinch
  if (ce) md8 <= ({mfs7,4'b0} >> xdif7)|sticky7; // xdif7 is a multiple of four
295
 
296
// sync control signals
297 64 robfinch
ft_delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8));
298
ft_delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8));
299
ft_delay #(.WID(N*4), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8));
300
ft_delay #(.WID(N*4), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8));
301
ft_delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8));
302 57 robfinch
 
303
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
304
// Clock #9
305
// Sort operands and perform add/subtract
306
// addition can generate an extra bit, subtract can't go negative
307
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
308
reg [(N+1)*4-1:0] oa9, ob9;
309
reg a_gt_b9;
310 64 robfinch
always_ff @(posedge clk)
311 57 robfinch
  if (ce) oa9 <= xa_gt_xb8 ? {siga8,4'b0} : md8;
312 64 robfinch
always_ff @(posedge clk)
313 57 robfinch
  if (ce) ob9 <= xa_gt_xb8 ? md8 : {sigb8,4'b0};
314 64 robfinch
always_ff @(posedge clk)
315 57 robfinch
  if (ce) a_gt_b9 <= a_gt_b8;
316
 
317
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
318
// Clock #10
319
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
320
wire realOp10;
321
reg [13:0] xo10;
322
 
323 64 robfinch
always_ff @(posedge clk)
324 57 robfinch
  if (ce) oaa10 <= a_gt_b9 ? oa9 : ob9;
325 64 robfinch
always_ff @(posedge clk)
326 57 robfinch
  if (ce) obb10 <= a_gt_b9 ? ob9 : oa9;
327 64 robfinch
ft_delay #(.WID(1), .DEP(8)) udly10a (.clk(clk), .ce(ce), .i(realOp2), .o(realOp10));
328
ft_delay #(.WID(14), .DEP(6)) udly10b (.clk(clk), .ce(ce), .i(xo4), .o(xo10));
329 57 robfinch
 
330
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
331
// Clock #11
332
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
333 64 robfinch
wire [(N+1)*4-1:0] mab11;
334
wire mab11c;
335 57 robfinch
wire [N*4-1:0] siga11, sigb11;
336
wire abInf11;
337
wire aNan11, bNan11;
338 64 robfinch
wire xoinf11;
339 57 robfinch
wire op11;
340
 
341 64 robfinch
ft_delay #(.WID(1), .DEP(8+RIP_STAGES)) udly11a (.clk(clk), .ce(ce), .i(aInf3&bInf3), .o(abInf11));
342
ft_delay #(.WID(1), .DEP(10+RIP_STAGES)) udly11c (.clk(clk), .ce(ce), .i(au.nan), .o(aNan11));
343
ft_delay #(.WID(1), .DEP(10+RIP_STAGES)) udly11d (.clk(clk), .ce(ce), .i(bu.nan), .o(bNan11));
344
ft_delay #(.WID(1), .DEP(3+RIP_STAGES)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11));
345
ft_delay #(.WID(N*4), .DEP(3+RIP_STAGES)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11));
346
ft_delay #(.WID(N*4), .DEP(3+RIP_STAGES)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11));
347
ft_delay #(.WID(1), .DEP(1+RIP_STAGES)) udly11h (.clk(clk), .ce(ce), .i(xo10==14'h2FFF), .o(xoinf11));
348
ft_delay #(.WID((N+1)*4+1), .DEP(1+RIP_STAGES)) udly11i (.clk(clk), .ce(ce), .i(realOp10 ? {odd10c,odd10} : {oss10c,oss10}), .o({mab11c,mab11}));
349 57 robfinch
 
350
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
351 64 robfinch
// Clock #12+RIP_STAGES
352 57 robfinch
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
353
reg [(N+1)*4*2-1:0] mo12;       // mantissa output
354
reg nan12;
355
reg qnan12;
356
reg infinity12;
357
wire sxo11;
358
wire so11;
359 64 robfinch
ft_delay #(.WID(1), .DEP(9)) udly12a (.clk(clk), .ce(ce), .i(sxo2), .o(sxo11));
360
ft_delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
361 57 robfinch
 
362 64 robfinch
always_ff @(posedge clk)
363 57 robfinch
if (ce)
364
        nan12 <= aNan11|bNan11;
365
 
366 64 robfinch
always_ff @(posedge clk)
367 57 robfinch
if (ce) begin
368
        infinity12 <= 1'b0;
369
        qnan12 <= 1'b0;
370
        casez({abInf11,aNan11,bNan11,xoinf11})
371
        4'b1???:        // inf +/- inf - generate QNaN on subtract, inf on add
372
                if (op11) begin
373
                        mo12 <= {4'h9,{(N+1)*4*2-4{1'd0}}};
374
                        qnan12 <= 1'b1;
375
                end
376
                else begin
377
                        mo12 <= {(N+1)*2{4'h9}};
378
                        infinity12 <= 1'b1;
379
                end
380
        4'b01??:        mo12 <= {4'b0,siga11[107:0],{(N+1)*4{1'd0}}};
381
        4'b001?:        mo12 <= {4'b0,sigb11[107:0],{(N+1)*4{1'd0}}};
382
        4'b0001:        begin mo12 <= {(N+1)*4*2{1'd0}}; infinity12 <= 1'b1; end
383
        default:        mo12 <= {3'b0,mab11c,mab11,{N*4{1'd0}}};        // mab has an extra lead bit and four trailing bits
384
        endcase
385
end
386
 
387
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
388
// Clock #13
389
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
390
wire so;                        // sign output
391
wire [15:0] xo; // de normalized exponent output
392
wire [(N+1)*4*2-1:0] mo;        // mantissa output
393
 
394 64 robfinch
ft_delay #(.WID(1), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(nan12), .o(o.nan) );
395
ft_delay #(.WID(1), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(qnan12), .o(o.qnan) );
396
ft_delay #(.WID(1), .DEP(1)) u13e (.clk(clk), .ce(ce), .i(infinity12), .o(o.infinity) );
397
ft_delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(o.sign));
398
ft_delay #(.WID(14), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(o.exp));
399
ft_delay #(.WID((N+1)*4*2), .DEP(1)) u13f (.clk(clk), .ce(ce), .i(mo12), .o(o.sig));
400
ft_delay #(.WID(1), .DEP(1)) udly13g (.clk(clk), .ce(ce), .i(1'b0), .o(o.snan));
401 57 robfinch
 
402
endmodule
403
 
404
 
405
module DFPAddsub128nr(clk, ce, rm, op, a, b, o);
406
input clk;              // system clock
407
input ce;               // core clock enable
408
input [2:0] rm; // rounding mode
409
input op;               // operation 0 = add, 1 = subtract
410
input DFP128 a; // operand a
411
input DFP128 b; // operand b
412
output DFP128 o;        // output
413
 
414
wire DFP128UD o1;
415
wire DFP128UN fpn0;
416
 
417
DFPAddsub128            u1 (clk, ce, rm, op, a, b, o1);
418
DFPNormalize128 u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
419
DFPRound128             u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
420
 
421
endmodule

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