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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPAddsub96.sv] - Blame information for rev 84

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1 75 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      DFPAddsub96.sv
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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39
import DFPPkg::*;
40
 
41
module DFPAddsub96(clk, ce, rm, op, a, b, o);
42
input clk;
43
input ce;
44
input [2:0] rm;
45
input op;
46
input DFP96 a;
47
input DFP96 b;
48
output DFP96UD o;
49
localparam N=25;                        // number of BCD digits
50
localparam RIP_STAGES = 3;
51
 
52
parameter TRUE = 1'b1;
53
parameter FALSE = 1'b0;
54
 
55
DFP96U au;
56
DFP96U bu;
57
 
58
DFPUnpack96 u00 (a, au);
59
DFPUnpack96 u01 (b, bu);
60
 
61
reg [(N+1)*4-1:0] oaa10;
62
reg [(N+1)*4-1:0] obb10;
63
wire [(N+1)*4-1:0] oss10;
64
wire oss10c;
65
 
66 80 robfinch
BCDAddNClk #(.N(N+1)) ubcdadn1
67 75 robfinch
(
68
        .clk(clk),
69 80 robfinch
        .a({4'h0,oaa10}),
70
        .b({4'h0,obb10}),
71 75 robfinch
        .o(oss10),
72
        .ci(1'b0),
73
        .co(oss10c)
74
);
75
 
76
wire [(N+1)*4-1:0] odd10;
77
wire odd10c;
78
 
79 80 robfinch
BCDSubtract #(.N(N+1)) ubcdsubn1
80 78 robfinch
(
81
        .clk(clk),
82 80 robfinch
        .a({4'h00,oaa10}),
83
        .b({4'h00,obb10}),
84 78 robfinch
        .o(odd10),
85 80 robfinch
        .sgn(odd10c)
86 78 robfinch
);
87 81 robfinch
 
88 75 robfinch
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
89
// Clock #1
90
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
91
reg op1;
92
reg az, bz;
93
always_ff @(posedge clk)
94
        op1 <= op;
95
always_ff @(posedge clk)
96
        az <= au.sig==100'd0 && au.exp==12'd0;
97
always_ff @(posedge clk)
98
        bz <= bu.sig==100'd0 && bu.exp==12'd0;
99
 
100
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
101
// Clock #2
102
//
103
// Figure out which operation is really needed an add or subtract ?
104
// If the signs are the same, use the orignal op,
105
// otherwise flip the operation
106
//  a +  b = add,+
107
//  a + -b = sub, so of larger
108
// -a +  b = sub, so of larger
109
// -a + -b = add,-
110
//  a -  b = sub, so of larger
111
//  a - -b = add,+
112
// -a -  b = add,-
113
// -a - -b = sub, so of larger
114
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
115
reg realOp2;
116
reg op2;
117
reg [13:0] xa2, xb2;
118
reg az2, bz2;
119
reg xa_gt_xb2;
120
reg [N*4-1:0] siga2, sigb2;
121
reg sigeq, siga_gt_sigb;
122
reg expeq;
123
 
124
always_ff @(posedge clk)
125
  if (ce) realOp2 = op1 ^ au.sign ^ bu.sign;
126
always_ff @(posedge clk)
127
  if (ce) op2 <= op1;
128
always_ff @(posedge clk)
129
  if (ce) xa2 <= au.exp;
130
always_ff @(posedge clk)
131
  if (ce) xb2 <= bu.exp;
132
always_ff @(posedge clk)
133
  if (ce) siga2 <= au.sig;
134
always_ff @(posedge clk)
135
  if (ce) sigb2 <= bu.sig;
136
always_ff @(posedge clk)
137
  if (ce) az2 <= az;
138
always_ff @(posedge clk)
139
  if (ce) bz2 <= bz;
140
always_ff @(posedge clk)
141
  if (ce)
142
        xa_gt_xb2 <= au.exp > bu.exp;
143
 
144
always_ff @(posedge clk)
145
  if (ce) sigeq <= au.sig==bu.sig;
146
always_ff @(posedge clk)
147
  if (ce) siga_gt_sigb <= au.sig > bu.sig;
148
always_ff @(posedge clk)
149
  if (ce) expeq <= au.exp==bu.exp;
150
 
151
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
152
// Clock #3
153
//
154
// Find out if the result will be zero.
155
// Determine which fraction to denormalize
156
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
157
//
158
reg [11:0] xa3, xb3;
159
reg resZero3;
160
reg xa_gt_xb3;
161
reg a_gt_b3;
162
reg op3;
163
wire sa3, sb3;
164
wire [2:0] rm3;
165
reg [N*4-1:0] mfs3;
166
 
167
always_ff @(posedge clk)
168
  if (ce) resZero3 <= (realOp2 & expeq & sigeq) ||      // subtract, same magnitude
169
                           (az2 & bz2);               // both a,b zero
170
always_ff @(posedge clk)
171
  if (ce) xa3 <= xa2;
172
always_ff @(posedge clk)
173
  if (ce) xb3 <= xb2;
174
always_ff @(posedge clk)
175
  if (ce) xa_gt_xb3 <= xa_gt_xb2;
176
always_ff @(posedge clk)
177
  if (ce) a_gt_b3 <= xa_gt_xb2 | (expeq & siga_gt_sigb);
178
always_ff @(posedge clk)
179
  if (ce) op3 <= op2;
180
always_ff @(posedge clk)
181
  if (ce) mfs3 = xa_gt_xb2 ? sigb2 : siga2;
182
 
183
ft_delay #(.WID(1), .DEP(2)) udly3c (.clk(clk), .ce(ce), .i(au.sign), .o(sa3));
184
ft_delay #(.WID(1), .DEP(2)) udly3d (.clk(clk), .ce(ce), .i(bu.sign), .o(sb3));
185
ft_delay #(.WID(3), .DEP(3)) udly3e (.clk(clk), .ce(ce), .i(rm), .o(rm3));
186 78 robfinch
ft_delay #(.WID(1), .DEP(3)) udly3f (.clk(clk), .ce(ce), .i(au.infinity), .o(aInf3));
187
ft_delay #(.WID(1), .DEP(3)) udly3g (.clk(clk), .ce(ce), .i(bu.infinity), .o(bInf3));
188 75 robfinch
 
189
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
190
// Clock #4
191
//
192
// Compute output exponent
193
//
194
// The output exponent is the larger of the two exponents,
195
// unless a subtract operation is in progress and the two
196
// numbers are equal, in which case the exponent should be
197
// zero.
198
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
199
 
200
reg [11:0] xa4, xb4;
201
reg [11:0] xo4;
202
reg xa_gt_xb4;
203
 
204
always_ff @(posedge clk)
205
  if (ce) xa4 <= xa3;
206
always_ff @(posedge clk)
207
  if (ce) xb4 <= xb3;
208
always_ff @(posedge clk)
209
        if (ce) xo4 <= resZero3 ? 12'd0 : xa_gt_xb3 ? xa3 : xb3;
210
always_ff @(posedge clk)
211
  if (ce) xa_gt_xb4 <= xa_gt_xb3;
212
 
213
// Compute output sign
214
reg so4;
215
always_comb
216
        case ({resZero3,sa3,op3,sb3})   // synopsys full_case parallel_case
217
        4'b0000: so4 <= 0;                      // + + + = +
218
        4'b0001: so4 <= !a_gt_b3;       // + + - = sign of larger
219
        4'b0010: so4 <= !a_gt_b3;       // + - + = sign of larger
220
        4'b0011: so4 <= 0;                      // + - - = +
221
        4'b0100: so4 <= a_gt_b3;                // - + + = sign of larger
222
        4'b0101: so4 <= 1;                      // - + - = -
223
        4'b0110: so4 <= 1;                      // - - + = -
224
        4'b0111: so4 <= a_gt_b3;                // - - - = sign of larger
225
        4'b1000: so4 <= 0;                      //  A +  B, sign = +
226
        4'b1001: so4 <= (rm3==3'd3);            //  A + -B, sign = + unless rounding down
227
        4'b1010: so4 <= (rm3==3'd3);            //  A - B, sign = + unless rounding down
228
        4'b1011: so4 <= 0;                      // A - -B, sign = +
229
        4'b1100: so4 <= (rm3==3'd3);            // -A -  -B, sign = + unless rounding down
230
        4'b1101: so4 <= 1;                      // -A + -B, sign = -
231
        4'b1110: so4 <= 1;                      // -A - +B, sign = -
232
        4'b1111: so4 <= (rm3==3'd3);            // A - B, sign = + unless rounding down
233
        endcase
234
 
235
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
236
// Clock #5
237
//
238
// Compute the difference in exponents, provides shift amount
239
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
240
reg [11:0] xdiff5;
241
always_ff @(posedge clk)
242
  if (ce) xdiff5 <= xa_gt_xb4 ? xa4 - xb4 : xb4 - xa4;
243
 
244
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
245
// Clock #6
246
//
247
// Compute the difference in exponents, provides shift amount
248
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
249
// If the difference in the exponent is 24 or greater (assuming 24 nybble dfp or
250
// less) then all of the bits will be shifted out to zero. There is no need to
251
// keep track of a difference more than 24.
252
reg [6:0] xdif6;
253
wire [N*4-1:0] mfs6;
254
always_ff @(posedge clk)
255
  if (ce) xdif6 <= xdiff5 > N ? N : xdiff5[6:0];
256
ft_delay #(.WID(N*4), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6));
257
 
258
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
259
// Clock #7
260
//
261
// Determine the sticky bit. The sticky bit is the bitwise or of all the bits
262
// being shifted out the right side. The sticky bit is computed here to
263
// reduce the number of regs required.
264
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
265
reg sticky6;
266
wire sticky7;
267
wire [7:0] xdif7;
268
wire [N*4-1:0] mfs7;
269
wire [8:0] xdif6a = {xdif6,2'b00};      // *4
270
integer n;
271
always @*
272
begin
273
        sticky6 = 1'b0;
274
        for (n = 0; n < N*4; n = n + 4)
275
                if (n <= xdif6a)
276
                        sticky6 = sticky6| mfs6[n]|mfs6[n+1]|mfs6[n+2]|mfs6[n+3];       // non-zero nybble
277
end
278
 
279
// register inputs to shifter and shift
280
delay1 #(1)  d16(.clk(clk), .ce(ce), .i(sticky6), .o(sticky7) );
281
delay1 #(9)  d15(.clk(clk), .ce(ce), .i(xdif6a),   .o(xdif7) );
282
delay1 #(N*4) d14(.clk(clk), .ce(ce), .i(mfs6),    .o(mfs7) );
283
 
284
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
285
// Clock #8
286
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
287
reg [(N+1)*4-1:0] md8;
288
wire [N*4-1:0] siga8, sigb8;
289
wire xa_gt_xb8;
290
wire a_gt_b8;
291
always_ff @(posedge clk)
292
  if (ce) md8 <= ({mfs7,4'b0} >> xdif7)|sticky7; // xdif7 is a multiple of four
293
 
294
// sync control signals
295
ft_delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8));
296
ft_delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8));
297
ft_delay #(.WID(N*4), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8));
298
ft_delay #(.WID(N*4), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8));
299
ft_delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8));
300
 
301
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
302
// Clock #9
303
// Sort operands and perform add/subtract
304
// addition can generate an extra bit, subtract can't go negative
305
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
306
reg [(N+1)*4-1:0] oa9, ob9;
307
reg a_gt_b9;
308
always_ff @(posedge clk)
309
  if (ce) oa9 <= xa_gt_xb8 ? {siga8,4'b0} : md8;
310
always_ff @(posedge clk)
311
  if (ce) ob9 <= xa_gt_xb8 ? md8 : {sigb8,4'b0};
312
always_ff @(posedge clk)
313
  if (ce) a_gt_b9 <= a_gt_b8;
314
 
315
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
316
// Clock #10
317
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
318
wire realOp10;
319
reg [11:0] xo10;
320
 
321
always_ff @(posedge clk)
322
  if (ce) oaa10 <= a_gt_b9 ? oa9 : ob9;
323
always_ff @(posedge clk)
324
  if (ce) obb10 <= a_gt_b9 ? ob9 : oa9;
325
ft_delay #(.WID(1), .DEP(8)) udly10a (.clk(clk), .ce(ce), .i(realOp2), .o(realOp10));
326
ft_delay #(.WID(12), .DEP(6)) udly10b (.clk(clk), .ce(ce), .i(xo4), .o(xo10));
327
 
328
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
329
// Clock #11
330
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
331
wire [(N+1)*4-1:0] mab11;
332
wire mab11c;
333
wire [N*4-1:0] siga11, sigb11;
334
wire abInf11;
335
wire aNan11, bNan11;
336
wire xoinf11;
337
wire op11;
338
 
339
ft_delay #(.WID(1), .DEP(8+RIP_STAGES)) udly11a (.clk(clk), .ce(ce), .i(aInf3&bInf3), .o(abInf11));
340
ft_delay #(.WID(1), .DEP(10+RIP_STAGES)) udly11c (.clk(clk), .ce(ce), .i(au.nan), .o(aNan11));
341
ft_delay #(.WID(1), .DEP(10+RIP_STAGES)) udly11d (.clk(clk), .ce(ce), .i(bu.nan), .o(bNan11));
342
ft_delay #(.WID(1), .DEP(3+RIP_STAGES)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11));
343
ft_delay #(.WID(N*4), .DEP(3+RIP_STAGES)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11));
344
ft_delay #(.WID(N*4), .DEP(3+RIP_STAGES)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11));
345 81 robfinch
ft_delay #(.WID(1), .DEP(1+RIP_STAGES)) udly11h (.clk(clk), .ce(ce), .i(xo10==12'hBFF), .o(xoinf11));
346 75 robfinch
ft_delay #(.WID((N+1)*4+1), .DEP(1+RIP_STAGES)) udly11i (.clk(clk), .ce(ce), .i(realOp10 ? {odd10c,odd10} : {oss10c,oss10}), .o({mab11c,mab11}));
347
 
348
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
349
// Clock #12+RIP_STAGES
350
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
351
reg [(N+1)*4*2-1:0] mo12;       // mantissa output
352
reg nan12;
353
reg qnan12;
354
reg infinity12;
355
wire so11;
356
ft_delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
357
 
358
always_ff @(posedge clk)
359
if (ce)
360
        nan12 <= aNan11|bNan11;
361
 
362
always_ff @(posedge clk)
363
if (ce) begin
364
        infinity12 <= 1'b0;
365
        qnan12 <= 1'b0;
366
        casez({abInf11,aNan11,bNan11,xoinf11})
367
        4'b1???:        // inf +/- inf - generate QNaN on subtract, inf on add
368
                if (op11) begin
369
                        mo12 <= {4'h9,{(N+1)*4*2-4{1'd0}}};
370
                        qnan12 <= 1'b1;
371
                end
372
                else begin
373
                        mo12 <= {(N+1)*2{4'h9}};
374
                        infinity12 <= 1'b1;
375
                end
376
        4'b01??:        mo12 <= {4'b0,siga11[87:0],{(N+1)*4{1'd0}}};
377
        4'b001?:        mo12 <= {4'b0,sigb11[87:0],{(N+1)*4{1'd0}}};
378
        4'b0001:        begin mo12 <= {(N+1)*4*2{1'd0}}; infinity12 <= 1'b1; end
379
        default:        mo12 <= {3'b0,mab11c,mab11,{N*4{1'd0}}};        // mab has an extra lead bit and four trailing bits
380
        endcase
381
end
382
 
383
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
384
// Clock #13
385
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
386
 
387
ft_delay #(.WID(1), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(nan12), .o(o.nan) );
388
ft_delay #(.WID(1), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(qnan12), .o(o.qnan) );
389
ft_delay #(.WID(1), .DEP(1)) u13e (.clk(clk), .ce(ce), .i(infinity12), .o(o.infinity) );
390
ft_delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(o.sign));
391
ft_delay #(.WID(12), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(o.exp));
392
ft_delay #(.WID((N+1)*4*2), .DEP(1)) u13f (.clk(clk), .ce(ce), .i(mo12), .o(o.sig));
393
ft_delay #(.WID(1), .DEP(1)) udly13g (.clk(clk), .ce(ce), .i(1'b0), .o(o.snan));
394
 
395
endmodule
396
 
397
 
398
module DFPAddsub96nr(clk, ce, rm, op, a, b, o);
399
input clk;              // system clock
400
input ce;               // core clock enable
401
input [2:0] rm; // rounding mode
402
input op;               // operation 0 = add, 1 = subtract
403
input DFP96 a;  // operand a
404
input DFP96 b;  // operand b
405
output DFP96 o; // output
406
 
407
wire DFP96UD o1;
408
wire DFP96UN fpn0;
409
 
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DFPAddsub96             u1 (clk, ce, rm, op, a, b, o1);
411
DFPNormalize96  u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
412
DFPRound96              u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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414
endmodule

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