OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPCompare96.sv] - Blame information for rev 80

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 75 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2020-2022  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch@finitron.ca
6
//       ||
7
//
8
//      DFPCompare96.sv
9
//
10
// BSD 3-Clause License
11
// Redistribution and use in source and binary forms, with or without
12
// modification, are permitted provided that the following conditions are met:
13
//
14
// 1. Redistributions of source code must retain the above copyright notice, this
15
//    list of conditions and the following disclaimer.
16
//
17
// 2. Redistributions in binary form must reproduce the above copyright notice,
18
//    this list of conditions and the following disclaimer in the documentation
19
//    and/or other materials provided with the distribution.
20
//
21
// 3. Neither the name of the copyright holder nor the names of its
22
//    contributors may be used to endorse or promote products derived from
23
//    this software without specific prior written permission.
24
//
25
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
29
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35
//
36
// ============================================================================
37
 
38
import DFPPkg::*;
39
 
40
module DFPCompare96(a, b, o);
41
input DFP96 a;
42
input DFP96 b;
43
output reg [11:0] o ='d0;
44 80 robfinch
localparam N=25;                        // number of BCD digits
45 75 robfinch
 
46
parameter TRUE = 1'b1;
47
parameter FALSE = 1'b0;
48
 
49
DFP96U au;
50
DFP96U bu;
51
 
52
DFPUnpack96 u00 (a, au);
53
DFPUnpack96 u01 (b, bu);
54
 
55
reg sa, sb;
56
always_comb
57
        sa = au.sign;
58
always_comb
59
        sb = bu.sign;
60
wire az = ~|{au.exp,au.sig};
61
wire bz = ~|{bu.exp,bu.sig};
62
wire unordered = au.nan | bu.nan;
63
 
64
wire eq = !unordered & ((az & bz) || (a==b));  // special test for zero
65
wire gt1 = {au.exp,au.sig} > {bu.exp,bu.sig};
66
wire lt1 = {au.exp,au.sig} < {bu.exp,bu.sig};
67
 
68
wire lt = sa ^ sb ? sa & !(az & bz): sa ? gt1 : lt1;
69
 
70
always_comb
71
begin
72
        o[0] = eq;
73
        o[1] = lt;
74
        o[2] = lt|eq;
75
        o[3] = lt1;
76
        o[4] = unordered;
77
        o[5] = ~eq;
78
        o[6] = ~lt;
79
        o[7] = ~(lt|eq);
80
        o[8] = ~lt1;
81
        o[9] = ~unordered;
82
        o[10] = 1'b0;
83
        o[11] = lt;
84
end
85
 
86
// an unorder comparison will signal a nan exception
87
//assign nanx = op!=`FCOR && op!=`FCUN && unordered;
88
 
89
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.