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// ============================================================================

//        __

//   \\__/ o\    (C) 2020  Robert Finch, Waterloo

//    \  __ /    All rights reserved.

//     \/_//     robfinch@finitron.ca

//       ||

//

//      DFPDecompose.sv

//

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// ============================================================================

module DFPDecompose(i, sgn, sx, exp, sig, xz, vz, inf, nan);

input [127:0] i;

output sgn;

output sx;

output [15:0] exp;

output [95:0] sig;

output xz;

output vz;

output inf;

output nan;

assign nan = i[127];

assign sgn = i[126];

assign inf = i[125];

assign sx = i[124];

assign exp = i[123:108];

assign sig = i[107:0];

assign xz = ~|exp;

assign vz = ~|{exp,sig};

endmodule

module DFPDecomposeReg(clk, ce, i, sgn, sx, exp, sig, xz, vz, inf, nan);

input clk;

input ce;

input [127:0] i;

output reg sgn;

output reg sx;

output reg [15:0] exp;

output reg [107:0] sig;

output reg xz;

output reg vz;

output reg inf;

output reg nan;

always @(posedge clk)

        if (ce) begin

                nan <= i[127];

                sgn <= i[126];

                inf <= i[125];

                sx <= i[124];

                exp <= i[123:108];

                sig <= i[107:0];

                xz <= ~|exp;

                vz <= ~|{exp,sig};

        end

endmodule