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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPMultiply.sv] - Blame information for rev 84

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      DFPMultiply.v
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//              - decimal floating point multiplier
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//              - can issue every clock cycle
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//              - parameterized width
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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//      Floating Point Multiplier
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//
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//      This multiplier handles denormalized numbers.
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//      The output format is of an internal expanded representation
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//      in preparation to be fed into a normalization unit, then
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//      rounding. Basically, it's the same as the regular format
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//      except the mantissa is doubled in size, the leading two
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//      bits of which are assumed to be whole bits.
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//
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//
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//      Floating Point Multiplier
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//
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//      Properties:
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//      +-inf * +-inf = -+inf   (this is handled by exOver)
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//      +-inf * 0     = QNaN
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//
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// ============================================================================
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import fp::*;
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//`define DFPMUL_PARALLEL       1'b1
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module DFPMultiply(clk, ce, ld, a, b, o, sign_exe, inf, overflow, underflow, done);
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parameter N=33;
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input clk;
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input ce;
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input ld;
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input  [N*4+16+4-1:0] a, b;
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output [(N+1)*4*2+16+4-1:0] o;
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output sign_exe;
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output inf;
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output overflow;
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output underflow;
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output done;
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parameter DELAY =
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  (FPWID == 128 ? 17 :
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  FPWID == 80 ? 17 :
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  FPWID == 64 ? 13 :
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  FPWID == 40 ? 8 :
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  FPWID == 32 ? 2 :
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  FPWID == 16 ? 2 : 2);
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reg [15:0] xo1;         // extra bit for sign
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reg [N*4*2-1:0] mo1;
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// constants
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wire [15:0] infXp = 16'h9999;   // infinite / NaN - all ones
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// The following is the value for an exponent of zero, with the offset
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// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
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// The following is a template for a quiet nan. (MSB=1)
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wire [N*4-1:0] qNaN  = {4'h1,{104{1'b0}}};
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// variables
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reg [N*4*2-1:0] sig1;
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wire [15:0] ex2;
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// Decompose the operands
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wire sa, sb;                    // sign bit
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wire [15:0] xa, xb;     // exponent bits
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wire sxa, sxb;
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wire [N*4-1:0] siga, sigb;
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wire a_dn, b_dn;                        // a/b is denormalized
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wire aNan, bNan, aNan1, bNan1;
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wire az, bz;
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wire aInf, bInf, aInf1, bInf1;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #1
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// - decode the input operands
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// - derive basic information
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// - calculate exponent
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// - calculate fraction
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// -----------------------------------------------------------
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// First clock
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// -----------------------------------------------------------
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reg under, over;
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reg [15:0] sum_ex, sum_ex1;
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reg sx0;
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wire done1;
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DFPDecompose u1a (.i(a), .sgn(sa), .sx(sxa), .exp(xa), .sig(siga), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );
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DFPDecompose u1b (.i(b), .sgn(sb), .sx(sxb), .exp(xb), .sig(sigb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );
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// Compute the sum of the exponents.
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// Exponents are sign-magnitude.
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wire [15:0] xapxb, xamxb, xbmxa;
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wire xapxbc, xamxbc, xbmxac;
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BCDAddN #(.N(4)) u1c (.ci(1'b0), .a(xa), .b(xb), .o(xapxb), .co(xapxbc));
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BCDSubN #(.N(4)) u1d (.ci(1'b0), .a(xa), .b(xb), .o(xamxb), .co(xamxbc));
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BCDSubN #(.N(4)) u1e (.ci(1'b0), .a(xb), .b(xa), .o(xbmxa), .co(xbmxac));
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BCDSubN #(.N(5)) u1h (.ci(1'b0), .a(20'h10000), .b(sum_ex1), .o(sum_ex2), .co());
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always @*
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        case({sxa,sxb})
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        2'b11:  begin sum_ex1 <= xapxb; over <= xapxbc; under <= 1'b0; sx0 <= sxa; end
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        2'b01:  begin sum_ex1 <= xbmxa; over <= 1'b0; under <= 1'b0; sx0 <= ~xbmxac; end
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        2'b10:  begin sum_ex1 <= xamxb; over <= 1'b0; under <= 1'b0; sx0 <= ~xamxbc; end
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        2'b00:  begin sum_ex1 <= xapxb; over <= 1'b0; under <= xapxbc; sx0 <= sxa; end
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        endcase
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// Take nine's complement if exponent sign changed.
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always @*
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        if ((sxa^sxb)) begin
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                if ((sxa & xamxbc) || (sxb & xbmxac))
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                        sum_ex <= sum_ex2;
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                else
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                        sum_ex <= sum_ex1;
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        end
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        else
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                sum_ex <= sum_ex1;
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wire [N*4*2-1:0] sigoo;
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`ifdef DFPMUL_PARALLEL
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BCDMul32 u1f (.a({20'h0,siga}),.b({20'h0,sigb}),.o(sigoo));
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`else
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dfmul #(.N(N)) u1g
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(
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        .clk(clk),
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        .ld(ld),
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        .a(siga),
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        .b(sigb),
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        .p(sigoo),
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        .done(done1)
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);
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`endif
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always @(posedge clk)
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  if (ce) sig1 <= sigoo[N*4*2-1:0];
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// Status
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wire under1, over1;
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delay #(.WID(16),.DEP(DELAY)) u3 (.clk(clk), .ce(ce), .i(sum_ex), .o(ex2) );
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delay #(.WID(1),.DEP(DELAY)) u2a (.clk(clk), .ce(ce), .i(aInf), .o(aInf1) );
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delay #(.WID(1),.DEP(DELAY)) u2b (.clk(clk), .ce(ce), .i(bInf), .o(bInf1) );
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delay #(.WID(1),.DEP(DELAY)) u6  (.clk(clk), .ce(ce), .i(under), .o(under1) );
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delay #(.WID(1),.DEP(DELAY)) u7  (.clk(clk), .ce(ce), .i(over), .o(over1) );
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// determine when a NaN is output
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wire qNaNOut;
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wire [N*4+16+4-1:0] a1,b1;
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delay #(.WID(1),.DEP(DELAY)) u5 (.clk(clk), .ce(ce), .i((aInf&bz)|(bInf&az)), .o(qNaNOut) );
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delay #(.WID(1),.DEP(DELAY)) u14 (.clk(clk), .ce(ce), .i(aNan), .o(aNan1) );
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delay #(.WID(1),.DEP(DELAY)) u15 (.clk(clk), .ce(ce), .i(bNan), .o(bNan1) );
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delay #(.WID(N*4+16+4),.DEP(DELAY))  u16 (.clk(clk), .ce(ce), .i(a), .o(a1) );
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delay #(.WID(N*4+16+4),.DEP(DELAY))  u17 (.clk(clk), .ce(ce), .i(b), .o(b1) );
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// -----------------------------------------------------------
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// Second clock
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// - correct xponent and mantissa for exceptional conditions
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// -----------------------------------------------------------
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wire so1, sx1;
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reg [3:0] st;
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wire done1a;
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delay #(.WID(1),.DEP(1)) u8 (.clk(clk), .ce(ce), .i(~(sa ^ sb)), .o(so1) );// two clock delay!
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delay #(.WID(1),.DEP(1)) u9 (.clk(clk), .ce(ce), .i(sx0), .o(sx1) );// two clock delay!
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always @(posedge clk)
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        if (ce)
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                casez({qNaNOut|aNan1|bNan1,aInf1,bInf1,over1,under1})
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                5'b1????:       xo1 = infXp;    // qNaN - infinity * zero
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                5'b01???:       xo1 = infXp;    // 'a' infinite
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                5'b001??:       xo1 = infXp;    // 'b' infinite
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                5'b0001?:       xo1 = infXp;    // result overflow
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                5'b00001:       xo1 = ex2[15:0];//0;            // underflow
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                default:        xo1 = ex2[15:0];        // situation normal
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                endcase
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// Force mantissa to zero when underflow or zero exponent when not supporting denormals.
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always @(posedge clk)
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        if (ce)
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                casez({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1|under1})
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                6'b1?????:  mo1 = {4'h1,a1[N*4-4-1:0],{N*4{1'b0}}};
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    6'b01????:  mo1 = {4'h1,b1[N*4-4-1:0],{N*4{1'b0}}};
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                6'b001???:      mo1 = {4'h1,qNaN|3'd4,{N*4{1'b0}}};     // multiply inf * zero
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                6'b0001??:      mo1 = 0;        // mul inf's
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                6'b00001?:      mo1 = 0;        // mul inf's
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                6'b000001:      mo1 = 0;        // mul overflow
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                default:        mo1 = sig1;
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                endcase
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always @(posedge clk)
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        if (ce) begin
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                st[3] <= aNan1|bNan1;
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                st[2] <= so1;
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                st[1] <= aInf|bInf|over;
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                st[0] <= sx1;
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        end
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delay #(.WID(1),.DEP(DELAY+1)) u10 (.clk(clk), .ce(ce), .i(sa & sb), .o(sign_exe) );
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delay1 u11 (.clk(clk), .ce(ce), .i(over1),  .o(overflow) );
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delay1 u12 (.clk(clk), .ce(ce), .i(over1),  .o(inf) );
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delay1 u13 (.clk(clk), .ce(ce), .i(under1), .o(underflow) );
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delay #(.WID(1),.DEP(3)) u18 (.clk(clk), .ce(ce), .i(done1), .o(done1a) );
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assign o = {st,xo1,mo1,8'h00};
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assign done = done1&done1a;
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endmodule
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// Multiplier with normalization and rounding.
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module DFPMultiplynr(clk, ce, ld, a, b, o, rm, sign_exe, inf, overflow, underflow, done);
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parameter N=33;
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input clk;
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input ce;
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input ld;
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input  [N*4+16+4-1:0] a, b;
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output [N*4+16+4-1:0] o;
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input [2:0] rm;
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output sign_exe;
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output inf;
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output overflow;
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output underflow;
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output done;
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wire done1, done1a;
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wire [(N+1)*4*2+16+4-1:0] o1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire [N*4+16+4-1+4:0] fpn0;
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DFPMultiply  u1 (clk, ce, ld, a, b, o1, sign_exe1, inf1, overflow1, underflow1, done1);
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DFPNormalize u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
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DFPRound     u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
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delay #(.WID(1),.DEP(11)) u10 (.clk(clk), .ce(ce), .i(done1), .o(done1a) );
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assign done = done1 & done1a;
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endmodule

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