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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPMultiply128.sv] - Blame information for rev 84

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1 64 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      DFPMultiply128.v
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//              - decimal floating point multiplier
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//              - parameterized width
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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//      Floating Point Multiplier
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//
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//      Properties:
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//      +-inf * +-inf = -+inf   (this is handled by exOver)
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//      +-inf * 0     = QNaN
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//
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// ============================================================================
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import DFPPkg::*;
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//`define DFPMUL_PARALLEL       1'b1
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module DFPMultiply128(clk, ce, ld, a, b, o, sign_exe, inf, overflow, underflow, done);
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localparam N=34;
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localparam DELAY = 2;
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input clk;
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input ce;
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input ld;
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input  DFP128 a, b;
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output DFP128UD o;
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output sign_exe;
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output inf;
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output overflow;
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output underflow;
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output done;
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reg [13:0] xo1;         // extra bit for sign
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reg [N*4*2-1:0] mo1;
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// constants
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wire [13:0] infXp = 14'h2FFF;   // infinite / NaN - all ones
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wire [13:0] bias = 14'h17FF;
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// The following is the value for an exponent of zero, with the offset
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// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
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// The following is a template for a quiet nan. (MSB=1)
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wire [N*4-1:0] qNaN  = {4'h1,{104{1'b0}}};
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// variables
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reg [N*4*2-1:0] sig1;
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wire [13:0] ex2;
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DFP128U au, bu;
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DFPUnpack128 u01 (a, au);
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DFPUnpack128 u02 (b, bu);
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// Decompose the operands
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wire sa, sb;                    // sign bit
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wire [13:0] xa, xb;     // exponent bits
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wire sxa, sxb;
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wire [N*4-1:0] siga, sigb;
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wire a_dn, b_dn;                        // a/b is denormalized
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wire aNan1, bNan1;
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wire az, bz;
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wire aInf1, bInf1;
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assign siga = au.sig;
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assign sigb = bu.sig;
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assign az = au.exp==14'h0 && au.sig==136'd0;
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assign bz = bu.exp==14'h0 && bu.sig==136'd0;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #1
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// - decode the input operands
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// - derive basic information
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// - calculate exponent
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// - calculate fraction
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// -----------------------------------------------------------
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// First clock
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// Compute the sum of the exponents.
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// -----------------------------------------------------------
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wire under, over;
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wire [15:0] sum_ex = au.exp + bu.exp - bias;
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reg sx0;
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wire done1;
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assign under = &sum_ex[15:14];
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assign over = sum_ex > 16'h2FFF;
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wire [N*4*2-1:0] sigoo;
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`ifdef DFPMUL_PARALLEL
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BCDMul32 u1f (.a({20'h0,siga}),.b({20'h0,sigb}),.o(sigoo));
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`else
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dfmul #(.N(N)) u1g
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(
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        .clk(clk),
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        .ld(ld),
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        .a(siga),
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        .b(sigb),
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        .p(sigoo),
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        .done(done1)
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);
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`endif
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always @(posedge clk)
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  if (ce) sig1 <= sigoo[N*4*2-1:0];
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// Status
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wire under1, over1;
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ft_delay #(.WID(14),.DEP(DELAY)) u3 (.clk(clk), .ce(ce), .i(sum_ex[13:0]), .o(ex2) );
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ft_delay #(.WID(1),.DEP(DELAY)) u2a (.clk(clk), .ce(ce), .i(au.infinity), .o(aInf1) );
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ft_delay #(.WID(1),.DEP(DELAY)) u2b (.clk(clk), .ce(ce), .i(bu.infinity), .o(bInf1) );
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ft_delay #(.WID(1),.DEP(DELAY)) u6  (.clk(clk), .ce(ce), .i(under), .o(under1) );
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ft_delay #(.WID(1),.DEP(DELAY)) u7  (.clk(clk), .ce(ce), .i(over), .o(over1) );
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// determine when a NaN is output
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wire qNaNOut;
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wire DFP128U a1,b1;
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wire asnan, bsnan, aqnan, bqnan;
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ft_delay #(.WID(1),.DEP(DELAY)) u5 (.clk(clk), .ce(ce), .i((au.infinity&bz)|(bu.infinity&az)), .o(qNaNOut) );
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ft_delay #(.WID(1),.DEP(DELAY)) u14 (.clk(clk), .ce(ce), .i(au.nan), .o(aNan1) );
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ft_delay #(.WID(1),.DEP(DELAY)) u15 (.clk(clk), .ce(ce), .i(bu.nan), .o(bNan1) );
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ft_delay #(.WID(1),.DEP(DELAY)) u18 (.clk(clk), .ce(ce), .i(au.snan), .o(asnan) );
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ft_delay #(.WID(1),.DEP(DELAY)) u19 (.clk(clk), .ce(ce), .i(bu.snan), .o(bsnan) );
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ft_delay #(.WID(1),.DEP(DELAY)) u18a (.clk(clk), .ce(ce), .i(au.qnan), .o(aqnan) );
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ft_delay #(.WID(1),.DEP(DELAY)) u19a (.clk(clk), .ce(ce), .i(bu.qnan), .o(bqnan) );
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ft_delay #(.WID($bits(a1)),.DEP(DELAY))  u16 (.clk(clk), .ce(ce), .i(a), .o(a1) );
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ft_delay #(.WID($bits(b1)),.DEP(DELAY))  u17 (.clk(clk), .ce(ce), .i(b), .o(b1) );
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// -----------------------------------------------------------
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// Second clock
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// - correct xponent and mantissa for exceptional conditions
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// -----------------------------------------------------------
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wire so1, sx1;
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reg [3:0] st;
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wire done1a;
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ft_delay #(.WID(1),.DEP(1)) u8 (.clk(clk), .ce(ce), .i(au.sign ^ bu.sign), .o(so1) );// two clock delay!
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always @(posedge clk)
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        if (ce)
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                casez({qNaNOut|aNan1|bNan1,aInf1,bInf1,over1,under1})
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                5'b1????:       xo1 = infXp;    // qNaN - infinity * zero
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                5'b01???:       xo1 = infXp;    // 'a' infinite
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                5'b001??:       xo1 = infXp;    // 'b' infinite
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                5'b0001?:       xo1 = infXp;    // result overflow
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                5'b00001:       xo1 = ex2[13:0];//0;            // underflow
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                default:        xo1 = ex2[13:0];        // situation normal
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                endcase
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// Force mantissa to zero when underflow or zero exponent when not supporting denormals.
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always @(posedge clk)
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        if (ce)
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                casez({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1|under1})
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                6'b1?????:  mo1 = {4'h1,a1[N*4-4-1:0],{N*4{1'b0}}};
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    6'b01????:  mo1 = {4'h1,b1[N*4-4-1:0],{N*4{1'b0}}};
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                6'b001???:      mo1 = {4'h1,qNaN|3'd4,{N*4{1'b0}}};     // multiply inf * zero
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                6'b0001??:      mo1 = 0;        // mul inf's
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                6'b00001?:      mo1 = 0;        // mul inf's
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                6'b000001:      mo1 = 0;        // mul overflow
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                default:        mo1 = sig1;
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                endcase
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ft_delay #(.WID(1),.DEP(DELAY+1)) u10 (.clk(clk), .ce(ce), .i(sa & sb), .o(sign_exe) );
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delay1 u11 (.clk(clk), .ce(ce), .i(over1),  .o(overflow) );
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delay1 u12 (.clk(clk), .ce(ce), .i(over1),  .o(inf) );
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delay1 u13 (.clk(clk), .ce(ce), .i(under1), .o(underflow) );
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ft_delay #(.WID(1),.DEP(3)) u18b (.clk(clk), .ce(ce), .i(done1), .o(done1a) );
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assign o.nan = aNan1|bNan1|qNaNOut;
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assign o.qnan = qNaNOut|aqnan|bqnan;
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assign o.snan = qNaNOut ? 1'b0 : asnan|bsnan;
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assign o.infinity = aInf1|bInf1|over;
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assign o.sign = so1;
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assign o.exp = xo1;
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assign o.sig = {mo1,8'h00};
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assign done = done1&done1a;
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endmodule
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// Multiplier with normalization and rounding.
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module DFPMultiply128nr(clk, ce, ld, a, b, o, rm, sign_exe, inf, overflow, underflow, done);
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localparam N=34;
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input clk;
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input ce;
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input ld;
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input  DFP128 a, b;
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output DFP128 o;
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input [2:0] rm;
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output sign_exe;
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output inf;
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output overflow;
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output underflow;
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output done;
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wire done1, done1a;
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DFP128UD o1;
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wire sign_exe1, inf1, overflow1, underflow1;
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DFP128UN fpn0;
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DFPMultiply128  u1 (clk, ce, ld, a, b, o1, sign_exe1, inf1, overflow1, underflow1, done1);
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DFPNormalize128 u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
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DFPRound128     u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
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ft_delay #(.WID(1),.DEP(12)) u10 (.clk(clk), .ce(ce), .i(done1), .o(done1a) );
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assign done = done1 & done1a;
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endmodule

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