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`timescale 1ns / 1ps

// ============================================================================

//        __

//   \\__/ o\    (C) 2020-2022  Robert Finch, Waterloo

//    \  __ /    All rights reserved.

//     \/_//     robfinch@finitron.ca

//       ||

//

//      DFPMultiply96.v

//              - decimal floating point multiplier

//              - parameterized width

//

//

// BSD 3-Clause License

// Redistribution and use in source and binary forms, with or without

// modification, are permitted provided that the following conditions are met:

//

// 1. Redistributions of source code must retain the above copyright notice, this

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//

//      Floating Point Multiplier

//

//      Properties:

//      +-inf * +-inf = -+inf   (this is handled by exOver)

//      +-inf * 0     = QNaN

//

// ============================================================================

import DFPPkg::*;

//`define DFPMUL_PARALLEL       1'b1

module DFPMultiply96(clk, ce, ld, a, b, o, sign_exe, inf, overflow, underflow, done);

localparam N=25;

localparam DELAY = 2;

input clk;

input ce;

input ld;

input  DFP96 a, b;

output DFP96UD o;

output sign_exe;

output inf;

output overflow;

output underflow;

output done;

reg [11:0] xo1;         // extra bit for sign

reg [N*4*2-1:0] mo1;

// constants

wire [11:0] infXp = 12'hBFF;    // infinite / NaN - all ones

wire [11:0] bias = 12'h5FF;

// The following is the value for an exponent of zero, with the offset

// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.

// The following is a template for a quiet nan. (MSB=1)

wire [N*4-1:0] qNaN  = {4'h1,{96{1'b0}}};

// variables

reg [N*4*2-1:0] sig1;

wire [13:0] ex2;

DFP96U au, bu;

DFPUnpack96 u01 (a, au);

DFPUnpack96 u02 (b, bu);

// Decompose the operands

wire sa, sb;                    // sign bit

wire [14:0] xa, xb;     // exponent bits

wire sxa, sxb;

wire [N*4-1:0] siga, sigb;

wire a_dn, b_dn;                        // a/b is denormalized

wire aNan1, bNan1;

wire az, bz;

wire aInf1, bInf1;

assign siga = au.sig;

assign sigb = bu.sig;

assign az = au.exp==12'h0 && au.sig==100'd0;

assign bz = bu.exp==12'h0 && bu.sig==100'd0;

// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

// Clock #1

// - decode the input operands

// - derive basic information

// - calculate exponent

// - calculate fraction

// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

// -----------------------------------------------------------

// First clock

// Compute the sum of the exponents.

// -----------------------------------------------------------

wire under, over;

wire [13:0] sum_ex = au.exp + bu.exp - bias;

reg sx0;

wire done1;

assign under = &sum_ex[13:12];

assign over = sum_ex > 14'hBFF && !under;

wire [N*4*2-1:0] sigoo;

`ifdef DFPMUL_PARALLEL

BCDMul32 u1f (.a({20'h0,siga}),.b({20'h0,sigb}),.o(sigoo));

`else

dfmul #(.N(N)) u1g

(

        .clk(clk),

        .ld(ld),

        .a(siga),

        .b(sigb),

        .p(sigoo),

        .done(done1)

);

`endif

always_ff @(posedge clk)

  if (ce) sig1 <= sigoo[N*4*2-1:0];

// Status

wire under1, over1;

ft_delay #(.WID(12),.DEP(DELAY)) u3 (.clk(clk), .ce(ce), .i(sum_ex[11:0]), .o(ex2) );

ft_delay #(.WID(1),.DEP(DELAY)) u2a (.clk(clk), .ce(ce), .i(au.infinity), .o(aInf1) );

ft_delay #(.WID(1),.DEP(DELAY)) u2b (.clk(clk), .ce(ce), .i(bu.infinity), .o(bInf1) );

ft_delay #(.WID(1),.DEP(DELAY)) u6  (.clk(clk), .ce(ce), .i(under), .o(under1) );

ft_delay #(.WID(1),.DEP(DELAY)) u7  (.clk(clk), .ce(ce), .i(over), .o(over1) );

// determine when a NaN is output

wire qNaNOut;

wire DFP96U a1,b1;

wire asnan, bsnan, aqnan, bqnan;

ft_delay #(.WID(1),.DEP(DELAY)) u5 (.clk(clk), .ce(ce), .i((au.infinity&bz)|(bu.infinity&az)), .o(qNaNOut) );

ft_delay #(.WID(1),.DEP(DELAY)) u14 (.clk(clk), .ce(ce), .i(au.nan), .o(aNan1) );

ft_delay #(.WID(1),.DEP(DELAY)) u15 (.clk(clk), .ce(ce), .i(bu.nan), .o(bNan1) );

ft_delay #(.WID(1),.DEP(DELAY)) u18 (.clk(clk), .ce(ce), .i(au.snan), .o(asnan) );

ft_delay #(.WID(1),.DEP(DELAY)) u19 (.clk(clk), .ce(ce), .i(bu.snan), .o(bsnan) );

ft_delay #(.WID(1),.DEP(DELAY)) u18a (.clk(clk), .ce(ce), .i(au.qnan), .o(aqnan) );

ft_delay #(.WID(1),.DEP(DELAY)) u19a (.clk(clk), .ce(ce), .i(bu.qnan), .o(bqnan) );

ft_delay #(.WID($bits(a1)),.DEP(DELAY))  u16 (.clk(clk), .ce(ce), .i(a), .o(a1) );

ft_delay #(.WID($bits(b1)),.DEP(DELAY))  u17 (.clk(clk), .ce(ce), .i(b), .o(b1) );

// -----------------------------------------------------------

// Second clock

// - correct xponent and mantissa for exceptional conditions

// -----------------------------------------------------------

wire so1, sx1;

reg [3:0] st;

wire done1a;

ft_delay #(.WID(1),.DEP(1)) u8 (.clk(clk), .ce(ce), .i(au.sign ^ bu.sign), .o(so1) );// two clock delay!

always_ff @(posedge clk)

        if (ce)

                casez({qNaNOut|aNan1|bNan1,aInf1,bInf1,over1,under1})

                5'b1????:       xo1 = infXp;    // qNaN - infinity * zero

                5'b01???:       xo1 = infXp;    // 'a' infinite

                5'b001??:       xo1 = infXp;    // 'b' infinite

                5'b0001?:       xo1 = infXp;    // result overflow

                5'b00001:       xo1 = ex2[11:0];//0;            // underflow

                default:        xo1 = ex2[11:0];        // situation normal

                endcase

// Force mantissa to zero when underflow or zero exponent when not supporting denormals.

always_ff @(posedge clk)

        if (ce)

                casez({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1|under1})

                6'b1?????:  mo1 = {4'h1,a1[N*4-4-1:0],{N*4{1'b0}}};

    6'b01????:  mo1 = {4'h1,b1[N*4-4-1:0],{N*4{1'b0}}};

                6'b001???:      mo1 = {4'h1,qNaN|3'd4,{N*4{1'b0}}};     // multiply inf * zero

                6'b0001??:      mo1 = 0;        // mul inf's

                6'b00001?:      mo1 = 0;        // mul inf's

                6'b000001:      mo1 = 0;        // mul overflow

                default:        mo1 = sig1;

                endcase

ft_delay #(.WID(1),.DEP(DELAY+1)) u10 (.clk(clk), .ce(ce), .i(sa & sb), .o(sign_exe) );

delay1 u11 (.clk(clk), .ce(ce), .i(over1),  .o(overflow) );

delay1 u12 (.clk(clk), .ce(ce), .i(over1),  .o(inf) );

delay1 u13 (.clk(clk), .ce(ce), .i(under1), .o(underflow) );

ft_delay #(.WID(1),.DEP(3)) u18b (.clk(clk), .ce(ce), .i(done1), .o(done1a) );

assign o.nan = aNan1|bNan1|qNaNOut;

assign o.qnan = qNaNOut|aqnan|bqnan;

assign o.snan = qNaNOut ? 1'b0 : asnan|bsnan;

assign o.infinity = aInf1|bInf1|over;

assign o.sign = so1;

assign o.exp = xo1;

assign o.sig = {mo1,8'h00};

assign done = done1&done1a;

endmodule

// Multiplier with normalization and rounding.

module DFPMultiply96nr(clk, ce, ld, a, b, o, rm, sign_exe, inf, overflow, underflow, done);

localparam N=25;

input clk;

input ce;

input ld;

input  DFP96 a, b;

output DFP96 o;

input [2:0] rm;

output sign_exe;

output inf;

output overflow;

output underflow;

output done;

wire done1, done1a;

DFP96UD o1;

wire sign_exe1, inf1, overflow1, underflow1;

DFP96UN fpn0;

DFPMultiply96  u1 (clk, ce, ld, a, b, o1, sign_exe1, inf1, overflow1, underflow1, done1);

DFPNormalize96 u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );

DFPRound96     u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );

delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));

delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));

delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));

delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));

ft_delay #(.WID(1),.DEP(12)) u10 (.clk(clk), .ce(ce), .i(done1), .o(done1a) );

assign done = done1 & done1a;

endmodule