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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPPack.sv] - Blame information for rev 75

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020-2021  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      DPDPack.sv
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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import DFPPkg::*;
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module DFPPack128(i, o);
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input DFP128U i;
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output DFP128 o;
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wire [109:0] enc_sig;
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DPDEncodeN #(.N(11)) u1 (i.sig[131:0], enc_sig);
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always_comb
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begin
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        // sign
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        o.sign <= i.sign;
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        // combo
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        if (i.qnan|i.snan)
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                o.combo <= 5'b11111;
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        else if (i.infinity)
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                o.combo <= 5'b11110;
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        else
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                o.combo <= i.sig[135:132] > 4'h7 ? {2'b11,i.exp[13:12],i.sig[132]} : {i.exp[13:12],i.sig[134:132]};
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        // exponent continuation
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        if (i.qnan)
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                o.expc <= {1'b0,i.exp[10:0]};
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        else if (i.snan)
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                o.expc <= {1'b1,i.exp[10:0]};
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        else
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                o.expc <= i.exp[11:0];
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        // significand continuation
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        o.sigc <= enc_sig;
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end
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endmodule
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module DFPPack96(i, o);
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input DFP96U i;
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output DFP96 o;
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wire [79:0] enc_sig;
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DPDEncodeN #(.N(8)) u1 (i.sig[95:0], enc_sig);
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always_comb
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begin
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        // sign
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        o.sign <= i.sign;
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        // combo
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        if (i.qnan|i.snan)
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                o.combo <= 5'b11111;
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        else if (i.infinity)
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                o.combo <= 5'b11110;
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        else
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                o.combo <= i.sig[99:96] > 4'h7 ? {2'b11,i.exp[11:10],i.sig[96]} : {i.exp[11:10],i.sig[98:96]};
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        // exponent continuation
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        if (i.qnan)
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                o.expc <= {1'b0,i.exp[8:0]};
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        else if (i.snan)
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                o.expc <= {1'b1,i.exp[8:0]};
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        else
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                o.expc <= i.exp[9:0];
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        // significand continuation
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        o.sigc <= enc_sig;
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end
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endmodule
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module DFPPack64(i, o);
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input DFP64U i;
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output DFP64 o;
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wire [49:0] enc_sig;
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DPDEncodeN #(.N(5)) u1 (i.sig[59:0], enc_sig);
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always_comb
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begin
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        // sign
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        o.sign <= i.sign;
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        // combo
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        if (i.qnan|i.snan)
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                o.combo <= 5'b11111;
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        else if (i.infinity)
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                o.combo <= 5'b11110;
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        else
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                o.combo <= i.sig[63:60] > 4'h7 ? {2'b11,i.exp[9:8],i.sig[60]} : {i.exp[9:8],i.sig[62:60]};
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        // exponent continuation
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        if (i.qnan)
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                o.expc <= {1'b0,i.exp[6:0]};
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        else if (i.snan)
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                o.expc <= {1'b1,i.exp[6:0]};
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        else
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                o.expc <= i.exp[7:0];
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        // significand continuation
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        o.sigc <= enc_sig;
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end
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endmodule

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