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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPPkg.sv] - Blame information for rev 69

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1 57 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020-2021  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      DFPPkg.sv
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//    - decimal floating point package
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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//
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//      This unit takes a floating point number in an intermediate
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// format and normalizes it. No normalization occurs
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// for NaN's or infinities. The unit has a two cycle latency.
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//
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// The mantissa is assumed to start with two whole bits on
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// the left. The remaining bits are fractional.
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//
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// The width of the incoming format is reduced via a generation
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// of sticky bit in place of the low order fractional bits.
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//
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// On an underflowed input, the incoming exponent is assumed
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// to be negative. A right shift is needed.
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// ============================================================================
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package DFPPkg;
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`define SUPPORT_DENORMALS       1'b1
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typedef struct packed
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{
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        logic sign;
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        logic [4:0] combo;
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        logic [14:0] expc;      // exponent continuation field
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        logic [139:0] sigc;     // significand continuation field
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} DFP160;
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// Packed 128 bit (storage) format
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typedef struct packed
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{
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        logic sign;
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        logic [4:0] combo;
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        logic [11:0] expc;      // exponent continuation field
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        logic [109:0] sigc;     // significand continuation field
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} DFP128;
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typedef logic [13:0] DFP128EXP;
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typedef logic [135:0] DFP128SIG;
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// Unpacked 128 bit format
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typedef struct packed
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{
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        logic nan;
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        logic qnan;
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        logic snan;
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        logic infinity;
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        logic sign;
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        logic [13:0] exp;
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        logic [135:0] sig;      // significand 34 digits
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} DFP128U;
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// Normalizer output to rounding, one extra digit
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typedef struct packed
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{
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        logic nan;
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        logic qnan;
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        logic snan;
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        logic infinity;
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        logic sign;
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        logic [13:0] exp;
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        logic [139:0] sig;      // significand 35 digits
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} DFP128UN;
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// 128-bit Double width significand, normalizer input
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typedef struct packed
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{
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        logic nan;
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        logic qnan;
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        logic snan;
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        logic infinity;
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        logic sign;
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        logic [13:0] exp;
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        logic [279:0] sig;      // significand 68+ 1 lead, 1-trail digit
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} DFP128UD;
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typedef logic [9:0] DFP64EXP;
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typedef logic [63:0] DFP64SIG;
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typedef struct packed
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{
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        logic sign;
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        logic [4:0] combo;
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        logic [7:0] expc;               // exponent continuation field
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        logic [49:0] sigc;      // significand continuation field
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} DFP64;
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typedef struct packed
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{
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        logic nan;
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        logic qnan;
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        logic snan;
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        logic infinity;
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        logic sign;
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        logic [9:0] exp;
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        logic [63:0] sig;               // significand 16 digits
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} DFP64U;
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typedef struct packed
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{
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        logic nan;
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        logic qnan;
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        logic snan;
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        logic infinity;
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        logic sign;
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        logic [9:0] exp;
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        logic [67:0] sig;               // significand 17 digits
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} DFP64UN;
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typedef struct packed
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{
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        logic nan;
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        logic qnan;
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        logic snan;
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        logic infinity;
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        logic sign;
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        logic [9:0] exp;
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        logic [127:0] sig;              // significand 32 digits
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} DFP64UD;
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endpackage

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