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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPRound.sv] - Blame information for rev 82

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      DFPRound.sv
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//    - decimal floating point rounding unit
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//    - parameterized width
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//    - IEEE 754 representation
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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import fp::*;
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`ifdef MIN_LATENCY
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`define PIPE_ADV  *
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`else
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`define PIPE_ADV  (posedge clk)
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`endif
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module DFPRound(clk, ce, rm, i, o);
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parameter N=33;
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input clk;
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input ce;
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input [2:0] rm;                 // rounding mode
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input [N*4+16+4+4-1:0] i;               // intermediate format input
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output [N*4+16+4-1:0] o;                // rounded output
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parameter ROUND_CEILING = 3'd0;
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parameter ROUND_FLOOR = 3'd1;
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parameter ROUND_HALF_UP = 3'd2;
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parameter ROUND_HALF_EVEN = 3'd3;
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parameter ROUND_DOWN = 3'd4;
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//------------------------------------------------------------
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// variables
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wire [3:0] so;
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wire [15:0] xo;
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reg  [N*4-1:0] mo;
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reg [15:0] xo1;
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reg [N*4-1:0] mo1;
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wire xInf = i[N*4+16+4-1:(N+1)*4]==16'h9999;
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wire so0 = i[N*4+16+4-2];
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assign o = {so,xo,mo};
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wire [3:0] l = i[7:4];
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wire [3:0] r = i[3:0];
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reg rnd;
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//------------------------------------------------------------
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// Clock #1
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// - determine round amount (add 1 or 0)
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//------------------------------------------------------------
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always @`PIPE_ADV
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if (ce) xo1 <= i[N*4+16+4-1:(N+1)*4];
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always @`PIPE_ADV
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if (ce) mo1 <= i[(N+1)*4-1:4];
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// Compute the round bit
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// Infinities and NaNs are not rounded!
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always @`PIPE_ADV
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if (ce)
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        if (|so[1:0])
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                rnd = 1'b0;
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        else
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                case (rm)
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                ROUND_CEILING:  rnd <= (r == 4'd0 || so[2]==1'b0) ? 1'b0 : 1'b1;
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                ROUND_FLOOR:            rnd <= (r == 4'd0 || so[2]==1'b1) ? 1'b0 : 1'b1;
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                ROUND_HALF_UP:  rnd <= r >= 4'h5;
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                ROUND_HALF_EVEN:        rnd <= r==4'h5 ? l[0] : r > 4'h5 ? 1'b1 : 1'b0;
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                ROUND_DOWN:                     rnd <= 1'b0;
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                default:                                rnd <= 1'b0;
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                endcase
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//------------------------------------------------------------
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// Clock #2
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// round the number, check for carry
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// note: inf. exponent checked above (if the exponent was infinite already, then no rounding occurs as rnd = 0)
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// note: exponent increments if there is a carry (can only increment to infinity)
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//------------------------------------------------------------
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wire [N*4+16+4-1-4:0] rounded1;
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wire co1;
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BCDAddN #(.N(N+4)) ubcdan1
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(
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        .ci(1'b0),
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        .a({xo1,mo1}),
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        .b({{N*4+16+4-1-4{1'd0}},rnd}),
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        .o(rounded1),
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        .co(co1)
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);
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reg [N*4+16+4-1-4:0] rounded2;
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reg carry2;
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reg rnd2;
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reg dn2;
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wire [15:0] xo2;
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always @`PIPE_ADV
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        if (ce) rounded2 <= rounded1;
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always @`PIPE_ADV
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        if (ce) carry2 <= co1;
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always @`PIPE_ADV
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        if (ce) rnd2 <= rnd;
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always @`PIPE_ADV
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        if (ce) dn2 <= !(|xo1);
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assign xo2 = rounded2[N*4+16+4-1-4:N*4];
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//------------------------------------------------------------
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// Clock #3
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// - shift mantissa if required.
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//------------------------------------------------------------
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`ifdef MIN_LATENCY
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assign so = i[N*4+16+4+3:N*4+16+4];
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assign xo = xo2;
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`else
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delay3 #(4) u21 (.clk(clk), .ce(ce), .i(i[N*4+16+4+3:N*4+16+4]), .o(so));
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delay1 #(16) u22 (.clk(clk), .ce(ce), .i(xo2), .o(xo));
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`endif
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always @`PIPE_ADV
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if (ce)
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        casez({rnd2,xo2==16'h9999,carry2,dn2})
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        4'b0??0:        mo <= mo1[N*4-1:0];                                                     // not rounding, not denormalized
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        4'b0??1:        mo <= mo1[N*4-1:0];                                                     // not rounding, denormalized
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        4'b1000:        mo <= rounded2[N*4-1: 0];                               // exponent didn't change, number was normalized
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        4'b1001:        mo <= rounded2[N*4-1: 0];                               // exponent didn't change, but number was denormalized
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        4'b1010:        mo <= {4'h1,rounded2[N*4-1: 4]};        // exponent incremented (new MSD generated), number was normalized
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        4'b1011:        mo <= rounded2[N*4-1:0];                                        // exponent incremented (new MSB generated), number was denormalized, number became normalized
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        4'b11??:        mo <= {N*4{1'd0}};                                                                      // number became infinite, no need to check carry etc., rnd would be zero if input was NaN or infinite
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        endcase
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endmodule

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