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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPUnpack.sv] - Blame information for rev 79

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      DPDUnpack.sv
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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import DFPPkg::*;
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module DFPUnpack128(i, o);
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input DFP128 i;
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output DFP128U o;
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assign o.sign = i.sign;
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assign o.exp = {i.combo[4:3]==2'b11 ? i.combo[2:1] : i.combo[4:3],i.expc};
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assign o.nan = i.combo==5'b11111;
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assign o.qnan = i.combo==5'b11111 && i.expc[11]==1'b0;
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assign o.snan = i.combo==5'b11111 && i.expc[11]==1'b1;
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assign o.infinity = i.combo==5'b11110;
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DPDDecodeN #(.N(11)) u1 (i.sigc, o.sig[131:0]);
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assign o.sig[135:132] = i.combo[4:3]==2'b11 ? {3'b100,i.combo[0]} : {1'b0,i.combo[2:0]};
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endmodule
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module DFPUnpack96(i, o);
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input DFP96 i;
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output DFP96U o;
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assign o.sign = i.sign;
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assign o.exp = {i.combo[4:3]==2'b11 ? i.combo[2:1] : i.combo[4:3],i.expc};
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assign o.nan = i.combo==5'b11111;
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assign o.qnan = i.combo==5'b11111 && i.expc[9]==1'b0;
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assign o.snan = i.combo==5'b11111 && i.expc[9]==1'b1;
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assign o.infinity = i.combo==5'b11110;
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DPDDecodeN #(.N(8)) u1 (i.sigc, o.sig[95:0]);
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assign o.sig[99:96] = i.combo[4:3]==2'b11 ? {3'b100,i.combo[0]} : {1'b0,i.combo[2:0]};
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endmodule
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module DFPUnpack64(i, o);
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input DFP64 i;
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output DFP64U o;
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assign o.sign = i.sign;
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assign o.exp = {i.combo[4:3]==2'b11 ? i.combo[2:1] : i.combo[4:3],i.expc};
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assign o.nan = i.combo==5'b11111;
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assign o.qnan = i.combo==5'b11111 && i.expc[7]==1'b0;
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assign o.snan = i.combo==5'b11111 && i.expc[7]==1'b1;
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assign o.infinity = i.combo==5'b11110;
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DPDDecodeN #(.N(5)) u1 (i.sigc, o.sig[59:0]);
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assign o.sig[63:60] = i.combo[4:3]==2'b11 ? {3'b100,i.combo[0]} : {1'b0,i.combo[2:0]};
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endmodule

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