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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DPD1000Decode.sv] - Blame information for rev 55

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1 55 robfinch
 
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module DPD1000Decode(clk, i, o);
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input clk;
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input [9:0] i;
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output [11:0] o;
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reg [9:0] i1;
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genvar g;
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(* ram_style="block" *)
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reg [11:0] tbl [0:1023];
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generate begin : gDPDTbl
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for (g = 0; g < 1024; g = g + 1) begin
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        initial begin
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                tbl[g] = (g % 10) | (((g / 10) & 15) << 4) | (((g/100) & 15) << 8);
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        end
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end
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end
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endgenerate
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always @(posedge clk)
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        i1 <= i;
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assign o = tbl[i1];
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endmodule
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module DPDDecodeN(clk, i, o);
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parameter N=11;
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input clk;
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input [N*10-1:0] i;
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output [N*12-1:0] o;
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genvar g;
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generate begin : gDPD
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        for (g = 0; g < N; g = g + 1)
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                DPD1000Decode(clk, i[g*10+9:g*10], o[g*12+11:g*12]);
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end
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endgenerate
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endmodule

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