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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DPD1000Encode.sv] - Blame information for rev 55

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1 55 robfinch
 
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module DPD1000Encode(i, o);
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input [11:0] i;
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output [9:0] o;
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assign o = i[3:0] + i[7:4] * 10 + i[11:8] * 100;
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endmodule
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module DPD1000EncodeN(i, o);
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parameter N=11;
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input [N*12-1:0] i;
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output [N*10-1:0] o;
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genvar g;
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generate begin : gDPDEncodeN
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        for (g = 0; g < N; g = g + 1)
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                DPD1000Encode u1 (i[g*12+11:g*12],o[g*10+9:g*10]);
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end
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endgenerate
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endmodule

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