OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [F32ToF80.v] - Blame information for rev 54

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 29 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch<remove>@finitron.ca
6
//       ||
7
//
8
//
9
//
10
// This source file is free software: you can redistribute it and/or modify 
11
// it under the terms of the GNU Lesser General Public License as published 
12
// by the Free Software Foundation, either version 3 of the License, or     
13
// (at your option) any later version.                                      
14
//                                                                          
15
// This source file is distributed in the hope that it will be useful,      
16
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
17
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
18
// GNU General Public License for more details.                             
19
//                                                                          
20
// You should have received a copy of the GNU General Public License        
21
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
22
//                                                                          
23
// ============================================================================
24
 
25
`include "fpConfig.sv"
26
 
27
module F32ToF80(a, o);
28
input [31:0] a;
29
output [79:0] o;
30
 
31
reg signo;
32
reg [14:0] expo;
33
reg [63:0] mano;
34
 
35
assign o = {signo,expo,mano};
36
 
37
wire signi;
38
wire [7:0] expi;
39
wire [22:0] mani;
40
wire xinf;      // exponent infinite
41
wire vz;        // value zero
42
wire xz;        // exponent zero
43
 
44
fpDecomp #(32) u1 (.i(a), .sgn(signi), .exp(expi), .man(mani), .xinf(xinf), .xz(xz), .vz(vz) );
45
wire [5:0] lz;
46
cntlz32 u2 ({mani,9'b111111111}, lz);   // '1' bit already unhidden due to denormalized number
47
 
48
always @*
49
begin
50
  // sign out always just = sign in
51
  signo <= signi;
52
 
53
  // special check for zero
54
  if (vz) begin
55
    expo <= 1'd0;
56
    mano <= 1'd0;
57
  end
58
  // convert infinity / nan
59
  // infinity in = infinity out
60
  else if (xinf) begin
61
    expo <= 15'h7fff;
62
    mano <= {mani,41'b0};
63
  end
64
  // convert denormal
65
  // a denormal was really a number with an exponent of -126
66
  // this value is easily represented in the double format
67
  // it may be possible to normalize the value if it isn't
68
  // zero
69
  else if (xz) begin
70
    expo <= 15'h3fff - 8'h7e - lz;      // 32767 "zero" -1022 - lz
71
    mano <= {mani << (lz + 1), 41'd0};  // shift one more to hide leading '1'
72
  end
73
  // convert typical number
74
  // adjust exponent, copy mantissa
75
  else begin
76
    expo <= expi + 15'h3fff - 8'h7f;
77
    mano <= {mani,41'd0};
78
  end
79
end
80
 
81
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.