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# Verilog2

This directory is a newer version of the cores with the 'WID' parameter renamed to 'FPWID' to avoid conflicts with other modules.

"EXTRA_BITS" was removed.

There are two versions of the cores one in verilog the other in SystemVerilog. They can be distinguished by the filename extension. Include one or the other in a project as they are using the same module names. However, the verilog versions are not likely to be updated in the future.

The SystemVerilog versions of the cores import the fp package rather than using fpConfig and fpSize. It is a little cleaner.