OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [df96Toi.sv] - Blame information for rev 75

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 75 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2022  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch@finitron.ca
6
//       ||
7
//
8
//      df128Toi.sv
9
//  - convert decimal floating point to integer
10
//
11
// BSD 3-Clause License
12
// Redistribution and use in source and binary forms, with or without
13
// modification, are permitted provided that the following conditions are met:
14
//
15
// 1. Redistributions of source code must retain the above copyright notice, this
16
//    list of conditions and the following disclaimer.
17
//
18
// 2. Redistributions in binary form must reproduce the above copyright notice,
19
//    this list of conditions and the following disclaimer in the documentation
20
//    and/or other materials provided with the distribution.
21
//
22
// 3. Neither the name of the copyright holder nor the names of its
23
//    contributors may be used to endorse or promote products derived from
24
//    this software without specific prior written permission.
25
//
26
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
30
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
33
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36
//
37
// ============================================================================
38
 
39
import DFPPkg::*;
40
 
41
module df96Toi (rst, clk, ce, ld, op, i, o, overflow, done);
42
input rst;
43
input clk;
44
input ce;
45
input ld;
46
input op;                                               // 1 = signed, 0 = unsigned
47
input [95:0] i;         // float input
48
output [95:0] o;                // integer output
49
output overflow;
50
output done;
51
 
52
wire done1;
53
reg done2;
54
assign done = done1 & done2;
55
 
56
wire [95:0] sig;
57
 
58
DFP96U ui;
59
DFPUnpack96 uunpk1 (i, ui);
60
 
61
wire [95:0] maxInt = op ? {1'd0,{95{1'b1}}} : {96{1'b1}};               // maximum integer value
62
wire [11:0] zeroXp = 12'h5FF;
63
 
64
reg sgn;                                                                        // sign
65
always_ff @(posedge clk)
66
        if (ce) sgn = ui.sign;
67
wire [11:0] exp = ui.exp;               // exponent
68
 
69
wire iz = i[94:0]==0;                   // zero value (special)
70
 
71
wire [12:0] ovx = exp - zeroXp;
72
assign overflow  = ovx > 23 && !ovx[12];   // lots of numbers are too big - don't forget one less bit is available due to signed values
73
wire underflow = exp < zeroXp - 2'd1;                   // value less than 1/2
74
 
75
wire [7:0] shamt = 8'd128 - {(exp - zeroXp),2'd0};      // exp - zeroXp will be <= MSB
76
 
77
wire [128:0] o1 = {ui.sig,33'b0} >> shamt;      // keep an extra bit for rounding
78
wire [95:0] o2;         // round up
79
reg [95:0] o3;
80
 
81
DDBCDToBin #(.WID(96)) ub2b1
82
(
83
        .rst(rst),
84
        .clk(clk),
85
        .ld(ld),
86
        .bcd({o1[128:1]+o1[0]}),
87
        .bin(o2),
88
        .done(done1)
89
);
90
 
91
 
92
always @(posedge clk)
93
        if (ce) begin
94
                if (underflow|iz)
95
                        o3 <='d0;
96
                else if (overflow)
97
                        o3 <= maxInt;
98
                // value between 1/2 and 1 - round up
99
                else if (exp==zeroXp-1)
100
                        o3 <= 96'd1;
101
                // value > 1
102
                else
103
                        o3 <= o2;
104
        end
105
always @(posedge clk)
106
        if (ce) done2 <= done1;
107
 
108
assign o = (op & sgn) ? -o3 : o3;                                        // adjust output for correct signed value
109
 
110
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.