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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [df96Toi.sv] - Blame information for rev 86

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1 75 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      df128Toi.sv
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//  - convert decimal floating point to integer
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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import DFPPkg::*;
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module df96Toi (rst, clk, ce, ld, op, i, o, overflow, done);
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input rst;
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input clk;
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input ce;
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input ld;
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input op;                                               // 1 = signed, 0 = unsigned
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input [95:0] i;         // float input
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output [95:0] o;                // integer output
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output overflow;
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output done;
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wire done1;
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reg done2;
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assign done = done1 & done2;
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wire [95:0] sig;
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DFP96U ui;
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DFPUnpack96 uunpk1 (i, ui);
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wire [95:0] maxInt = op ? {1'd0,{95{1'b1}}} : {96{1'b1}};               // maximum integer value
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wire [11:0] zeroXp = 12'h5FF;
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reg sgn;                                                                        // sign
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always_ff @(posedge clk)
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        if (ce) sgn = ui.sign;
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wire [11:0] exp = ui.exp;               // exponent
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wire iz = i[94:0]==0;                   // zero value (special)
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wire [12:0] ovx = exp - zeroXp;
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assign overflow  = ovx > 23 && !ovx[12];   // lots of numbers are too big - don't forget one less bit is available due to signed values
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wire underflow = exp < zeroXp - 2'd1;                   // value less than 1/2
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wire [7:0] shamt = 8'd128 - {(exp - zeroXp),2'd0};      // exp - zeroXp will be <= MSB
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wire [128:0] o1 = {ui.sig,33'b0} >> shamt;      // keep an extra bit for rounding
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wire [95:0] o2;         // round up
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reg [95:0] o3;
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DDBCDToBin #(.WID(96)) ub2b1
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(
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        .rst(rst),
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        .clk(clk),
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        .ld(ld),
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        .bcd({o1[128:1]+o1[0]}),
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        .bin(o2),
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        .done(done1)
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);
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always @(posedge clk)
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        if (ce) begin
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                if (underflow|iz)
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                        o3 <='d0;
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                else if (overflow)
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                        o3 <= maxInt;
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                // value between 1/2 and 1 - round up
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                else if (exp==zeroXp-1)
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                        o3 <= 96'd1;
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                // value > 1
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                else
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                        o3 <= o2;
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        end
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always @(posedge clk)
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        if (ce) done2 <= done1;
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assign o = (op & sgn) ? -o3 : o3;                                        // adjust output for correct signed value
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endmodule

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