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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [dfdiv2.sv] - Blame information for rev 83

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1 80 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      dfdiv2.v
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//    Decimal Float divider primitive
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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module dfdiv2(clk, ld, a, b, q, r, done, lzcnt);
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parameter N=33;
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localparam FPWID = N*4;
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parameter RADIX = 10;
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localparam FPWID1 = FPWID;//((FPWID+2)/3)*3;    // make FPWIDth a multiple of three
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localparam DMSB = FPWID1-1;
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input clk;
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input ld;
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input [FPWID-1:0] a;
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input [FPWID-1:0] b;
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output reg [FPWID*2-1:0] q;
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output reg [FPWID-1:0] r;
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output reg done;
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output reg [7:0] lzcnt; // Leading zero digit count
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reg [2:0] st;
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parameter IDLE = 3'd0;
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parameter DDIN1 = 3'd1;
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parameter DDIN2 = 3'd2;
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parameter CALC = 3'd3;
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parameter DDO = 3'd4;
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parameter DONE = 3'd5;
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parameter DDIN3 = 3'd6;
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reg rstdd;
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reg ldddi,lddiv,ldddo;
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reg [1:0] ddidone,ddodone;
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wire ddadone,ddbdone,divdone,ddoqdone,ddordone;
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wire [N*4-1:0] dda, ddb;
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wire [N*4*2-1:0] qdiv;
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wire [N*4-1:0] rdiv;
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wire [N*4*2-1:0] qo,qo1;
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wire [N*4-1:0] ro;
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DDBCDToBin #(.WID(N*4)) uddi1
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(
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        .rst(rstdd),
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        .clk(clk),
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        .ld(ldddi),
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        .bcd(a),
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        .bin(dda),
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        .done(ddadone)
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);
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DDBCDToBin #(.WID(N*4)) uddi2
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(
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        .rst(rstdd),
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        .clk(clk),
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        .ld(ldddi),
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        .bcd(b),
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        .bin(ddb),
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        .done(ddbdone)
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);
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fpdivr2 #(.FPWID(N*4)) udiv1
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(
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        .clk_div(clk),
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        .ld(lddiv),
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        .a({{N*4{1'b0}},dda}),
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        .b({{N{1'b0}},ddb}),
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        .q(qdiv),
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        .r(rdiv),
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        .done(divdone),
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        .lzcnt()
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);
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DDBinToBCDFract #(.WID(N*4)) udd3
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(
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        .rst(rstdd),
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        .clk(clk),
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        .ld(ldddo),
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        .bin({qdiv[N*4-1:0],4'h0}),
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        .bcd(qo1),
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        .done(ddoqdone)
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);
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assign qo = {qdiv[N*4+3:N*4],qo1[N*4-1:4]};
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DDBinToBCDFract #(.WID(N*4)) udd4
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(
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        .rst(rstdd),
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        .clk(clk),
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        .ld(ldddo),
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        .bin(rdiv),
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        .bcd(ro),
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        .done(ddordone)
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);
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reg nz;
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reg [N-1:0] zc;
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genvar g;
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generate begin : glzcnt
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        for (g = N-1; g >= 0; g = g - 1)
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        always_comb
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                zc[g] = qo[g*4+3+N*4:g*4+N*4]==0;
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end
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endgenerate
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integer n;
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always_comb
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begin
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        nz = 1'b0;
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        lzcnt = 'd0;
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        for (n = N-1; n >= 0; n = n - 1)
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        begin
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                nz = nz | ~zc[n];
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                if (!nz)
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                        lzcnt = lzcnt + 1;
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        end
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end
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always_comb
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        lddiv <= ddidone==2'b11 && st==DDIN3;
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always_comb
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        ldddo <= divdone==1'b1 && st==CALC;
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always_ff @(posedge clk)
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begin
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        rstdd <= 1'b0;
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        ldddi <= 1'b0;
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case(st)
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IDLE:   ;
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DDIN1:
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        begin
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                ldddi <= 1'b1;
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                st <= DDIN2;
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        end
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DDIN2:
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        st <= DDIN3;
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DDIN3:
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        begin
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                if (ddadone) ddidone <= ddidone | {ddbdone,ddadone};
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                if (ddidone==2'b11)
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                        st <= CALC;
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        end
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CALC:
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        if (divdone)
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                st <= DDO;
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DDO:
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        begin
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                if (ddoqdone) ddodone <= ddodone | {ddordone,ddoqdone};
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                q <= qo;
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                r <= ro;
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                if (ddodone==2'b11)
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                        st <= DONE;
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        end
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DONE:
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        begin
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                done <= 1'b1;
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        end
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default:
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        st <= IDLE;
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endcase
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if (ld) begin
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        done <= 1'b0;
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        rstdd <= 1'b1;
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        ddidone <= 'd0;
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        ddodone <= 'd0;
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        st <= DDIN1;
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end
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end
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endmodule
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module dfdiv2_tb();
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reg clk;
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reg ld;
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reg [135:0] a, b;
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wire [271:0] q;
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wire [135:0] r;
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wire [7:0] lzcnt;
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initial begin
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        clk = 1'b0;
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        ld = 1'b0;
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        a = 136'h99_99999999_00000000_00000000_00000000;
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        b = 136'h50_00000000_00000000_00000000_00000000;
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        #20 ld = 1'b1;
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        #40 ld = 1'b0;
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end
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always #5 clk = ~clk;
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dfdiv2 #(.N(34)) u1 (
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        .clk(clk),
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        .ld(ld),
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        .a(a),
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        .b(b),
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        .q(q),
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        .r(r),
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        .done(done),
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        .lzcnt(lzcnt)
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);
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endmodule

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