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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [dfmul.sv] - Blame information for rev 55

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1 54 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      dfmul.v
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//    Decimal Float multiplier primitive
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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module dfmul(clk, ld, a, b, p, done);
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parameter N=33;
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localparam FPWID = N*4;
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parameter RADIX = 10;
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localparam FPWID1 = FPWID;//((FPWID+2)/3)*3;    // make FPWIDth a multiple of three
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localparam DMSB = FPWID1-1;
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input clk;
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input ld;
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input [FPWID-1:0] a;
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input [FPWID-1:0] b;
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output reg [FPWID*2-1:0] p;
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output reg done;
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reg [1:0] st;
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parameter PREP = 2'd0;
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parameter ADDN = 2'd1;
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parameter DONE = 2'd2;
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reg [3:0] cnt;                          // iteration count
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reg [7:0] dcnt;                         // digit count
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reg [9:0] clkcnt;
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reg [FPWID*2-1:0] pi = 0;
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reg [FPWID-1:0] ai = 0;
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reg [FPWID*2-1:0] bi = 0;
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wire [FPWID*2-1:0] sum;
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BCDAddN #(.N((FPWID*2)/4)) u1
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(
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        .ci(1'b0),
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        .a(pi),
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        .b(bi),
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        .o(sum),
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        .co()
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);
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always @(posedge clk)
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begin
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case(st)
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ADDN:
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        begin
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                clkcnt <= clkcnt + 1'd1;
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                if (ai[FPWID-1:FPWID-4]!=4'h0) begin
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                        pi <= sum;
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                        ai[FPWID-1:FPWID-4] <= ai[FPWID-1:FPWID-4] - 1'd1;
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                        cnt <= cnt + 1'd1;
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                end
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                else begin
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                        ai <= {ai,4'h0};
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                        bi <= {4'h0,bi[FPWID*2-1:4]};
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                        pi <= pi;
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                        dcnt <= dcnt - 1'd1;
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                        if (dcnt==6'd0)
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                                st <= DONE;
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                end
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        end
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DONE:
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        begin
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                p <= pi;
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                done <= 1'b1;
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        end
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default:
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        st <= ADDN;
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endcase
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if (ld) begin
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        clkcnt <= 10'd0;
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        cnt <= 4'd0;
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        dcnt <= (FPWID*2)/4;
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        pi <= {FPWID*2{1'b0}};
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        ai <= a;
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        bi <= {4'h0,b,{FPWID-4{1'b0}}};
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        st <= ADDN;
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        done <= 1'b0;
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end
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end
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endmodule
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module dfmul_tb();
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reg clk;
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reg ld;
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reg [107:0] a, b;
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wire [215:0] p;
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initial begin
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        clk = 1'b0;
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        ld = 1'b0;
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        a = 108'h099_00000000_00000000_00000000;
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        b = 108'h560_00000000_00000000_00000000;
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        #20 ld = 1'b1;
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        #40 ld = 1'b0;
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end
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always #5 clk = ~clk;
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dfmul #(27) u1 (
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        .clk(clk),
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        .ld(ld),
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        .a(a),
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        .b(b),
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        .p(p),
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        .done(done)
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);
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endmodule

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