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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [f2i.v] - Blame information for rev 78

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1 29 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      f2i.v
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//              - convert floating point to integer
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//              - single cycle latency floating point unit
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//              - parameterized FPWIDth
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//              - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//      i2f - convert integer to floating point
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//  f2i - convert floating point to integer
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//
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// ============================================================================
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`include "fpConfig.sv"
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module f2i(clk, ce, i, o, overflow);
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parameter FPWID = 32;
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`include "fpSize.sv"
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input clk;
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input ce;
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input [MSB:0] i;
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output [MSB:0] o;
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output overflow;
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wire [MSB:0] maxInt  = {MSB{1'b1}};              // maximum unsigned integer value
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wire [EMSB:0] zeroXp = {EMSB{1'b1}};     // simple constant - value of exp for zero
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// Decompose fp value
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reg sgn;                                                                        // sign
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always @(posedge clk)
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        if (ce) sgn = i[MSB];
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wire [EMSB:0] exp = i[MSB-1:FMSB+1];             // exponent
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wire [FMSB+1:0] man = {exp!=0,i[FMSB:0]};  // mantissa including recreate hidden bit
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wire iz = i[MSB-1:0]==0;                                  // zero value (special)
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assign overflow  = exp - zeroXp > MSB - `EXTRA_BITS;            // lots of numbers are too big - don't forget one less bit is available due to signed values
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wire underflow = exp < zeroXp - 1;                      // value less than 1/2
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wire [7:0] shamt = MSB - (exp - zeroXp); // exp - zeroXp will be <= MSB
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wire [MSB+1:0] o1 = {man,{EMSB+1{1'b0}},1'b0} >> shamt;  // keep an extra bit for rounding
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wire [MSB:0] o2 = o1[MSB+1:1] + o1[0];            // round up
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reg [MSB:0] o3;
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always @(posedge clk)
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        if (ce) begin
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                if (underflow|iz)
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                        o3 <= 0;
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                else if (overflow)
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                        o3 <= maxInt;
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                // value between 1/2 and 1 - round up
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                else if (exp==zeroXp-1)
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                        o3 <= 1;
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                // value > 1
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                else
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                        o3 <= o2;
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        end
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assign o = sgn ? -o3 : o3;                                      // adjust output for correct signed value
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endmodule
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module f2i_tb();
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wire ov0,ov1;
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wire [31:0] io0,io1;
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reg clk;
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initial begin
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        clk = 0;
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end
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always #10 clk = ~clk;
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f2i #(32) u1 (.clk(clk), .ce(1'b1), .i(32'h3F800000), .o(io1), .overflow(ov1) );
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f2i #(32) u2 (.clk(clk), .ce(1'b1), .i(32'h00000000), .o(io0), .overflow(ov0) );
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f2i #(80) u3 (.clk(clk), .ce(1'b1), .i(80'h3FF80000000000000000), .o(io1), .overflow(ov1) );
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endmodule

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