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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fcvtsq.v] - Blame information for rev 84

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1 29 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2016  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      fcvtsq.v
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//              - convert single precision to quad precision
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//              - zero latency
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//              - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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`include "fpConfig.sv"
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module fcvtsq(a, o);
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parameter FPWID = 128;
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`include "fpSize.sv"
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input [31:0] a;
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output reg [FPWID-1:0] o;
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wire sa;
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wire [7:0] xa;
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wire [22:0] ma;
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wire [23:0] fracta;
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wire adn;
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wire az;
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wire xaInf;
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wire xInf;
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wire aNan;
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fpDecomp #(32) u1a (.i(a), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
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always @*
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begin
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    o[127] <= a[31];    // sign bit
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casex({aNan,aInf,az,adn})
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// NaN in, NaN out
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4'b1xxx:
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    begin
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        o[126:111] <= 16'hFFFF;
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        o[110:103] <= a[22:15];
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        o[14:0] <= a[14:0];
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    end
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// Infinity in, infinity out
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4'bx1xx:
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    begin
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        o[126:111] <= 16'hFFFF;
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        o[110:0] <= 111'b0;
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    end
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// Zero in, zero out
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4'bxx1x:
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        o[126:0] <= 127'b0;
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// Denormal
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4'bxxx1:
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    begin
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        o[126:111] <= 16'h0000;
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        o[110:88] <= ma;
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    end
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default:
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    begin
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        o[126:111] <= xa + 16256;
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        o[110:88] <= ma;
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    end
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endcase
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end
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endmodule

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