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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpAddsub_L10.v] - Blame information for rev 61

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1 29 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      fpAddsub.v
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//    - floating point adder/subtracter
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//    - ten cycle latency
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//    - can issue every clock cycle
12
//    - parameterized FPWIDth
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//    - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
30
 
31
`include "fpConfig.sv"
32
 
33
module fpAddsub_L10(clk, ce, rm, op, a, b, o);
34
parameter FPWID = 128;
35
`include "fpSize.sv"
36
 
37
input clk;              // system clock
38
input ce;               // core clock enable
39
input [2:0] rm;  // rounding mode
40
input op;               // operation 0 = add, 1 = subtract
41
input [MSB:0] a; // operand a
42
input [MSB:0] b; // operand b
43
output [EX:0] o; // output
44
 
45
wire so;                        // sign output
46
wire [EMSB:0] xo;        // de normalized exponent output
47
reg [FX:0] mo;   // mantissa output
48
 
49
assign o = {so,xo,mo};
50
 
51
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
52
// Clock edge #1
53
// - Decompose inputs into more digestible values.
54
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
55
wire [MSB:0] a1;
56
wire [MSB:0] b1;
57
wire sa1, sb1;
58
wire [EMSB:0] xa1, xb1;
59
wire [FMSB:0] ma1, mb1;
60
wire [FMSB+1:0] fracta1, fractb1;
61
wire adn1, bdn1;                // a,b denormalized ?
62
wire xaInf1, xbInf1;
63
wire aInf1, bInf1;
64
wire aNan1, bNan1;
65
wire az1, bz1;  // operand a,b is zero
66
wire op1;
67
 
68
fpDecompReg #(FPWID) u1a (.clk(clk), .ce(ce), .i(a), .o(a1), .sgn(sa1), .exp(xa1), .man(ma1), .fract(fracta1), .xz(adn1), .vz(az1), .xinf(xaInf1), .inf(aInf1), .nan(aNan1) );
69
fpDecompReg #(FPWID) u1b (.clk(clk), .ce(ce), .i(b), .o(b1), .sgn(sb1), .exp(xb1), .man(mb1), .fract(fractb1), .xz(bdn1), .vz(bz1), .xinf(xbInf1), .inf(bInf1), .nan(bNan1) );
70
delay1 #(1)  dop1(.clk(clk), .ce(ce), .i(op), .o(op1) );
71
 
72
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
73
// Clock edge #2
74
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
75
reg xabeq2;
76
reg mabeq2;
77
reg anbz2;
78
reg xabInf2;
79
reg anbInf2;
80
wire [EMSB:0] xa2, xb2;
81
wire [FMSB:0] ma2, mb2;
82
// operands sign,exponent,mantissa
83
wire [FMSB+1:0] fracta2, fractb2;
84
wire az2, bz2;  // operand a,b is zero
85
reg xa_gt_xb2;
86
reg var2;
87
reg [EMSB:0] xad2;
88
reg [EMSB:0] xbd2;
89
reg realOp2;
90
 
91
delay1 #(EMSB+1)  dxa2(.clk(clk), .ce(ce), .i(xa1), .o(xa2) );
92
delay1 #(EMSB+1)  dxb2(.clk(clk), .ce(ce), .i(xb1), .o(xb2) );
93
delay1 #(FMSB+1)  dma2(.clk(clk), .ce(ce), .i(ma1), .o(ma2) );
94
delay1 #(FMSB+1)  dmb2(.clk(clk), .ce(ce), .i(mb1), .o(mb2) );
95
delay1 #(1)  daz2(.clk(clk), .ce(ce), .i(az1), .o(az2) );
96
delay1 #(1)  dbz2(.clk(clk), .ce(ce), .i(bz1), .o(bz2) );
97
delay1 #(FMSB+2)  dfracta2(.clk(clk), .ce(ce), .i(fracta1), .o(fracta2) );
98
delay1 #(FMSB+2)  dfractb2(.clk(clk), .ce(ce), .i(fractb1), .o(fractb2) );
99
 
100
always @(posedge clk)
101
        if (ce) xa_gt_xb2 <= xa1 > xb1;
102
always @(posedge clk)
103
        if (ce) var2 <= (xa1==xb1 && ma1 > mb1);
104
always @(posedge clk)
105
        if (ce) xad2 <= xa1|adn1;       // operand a exponent, compensated for denormalized numbers
106
always @(posedge clk)
107
        if (ce) xbd2 <= xb1|bdn1;       // operand b exponent, compensated for denormalized numbers
108
always @(posedge clk)
109
        if (ce) xabeq2 <= xa1==xb1;
110
always @(posedge clk)
111
        if (ce) mabeq2 <= ma1==mb1;
112
always @(posedge clk)
113
        if (ce) anbz2 <= az1 & bz1;
114
always @(posedge clk)
115
        if (ce) xabInf2 <= xaInf1 & xbInf1;
116
always @(posedge clk)
117
        if (ce) anbInf2 <= aInf1 & bInf1;
118
 
119
// Figure out which operation is really needed an add or
120
// subtract ?
121
// If the signs are the same, use the orignal op,
122
// otherwise flip the operation
123
//  a +  b = add,+
124
//  a + -b = sub, so of larger
125
// -a +  b = sub, so of larger
126
// -a + -b = add,-
127
//  a -  b = sub, so of larger
128
//  a - -b = add,+
129
// -a -  b = add,-
130
// -a - -b = sub, so of larger
131
always @(posedge clk)
132
        if (ce) realOp2 <= op1 ^ sa1 ^ sb1;
133
 
134
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
135
// Clock edge #3
136
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
137
wire [EMSB:0] xa3, xb3;
138
wire xa_gt_xb3;
139
reg x_gt_b3;
140
wire xabInf3;
141
wire sa3,sb3;
142
wire op3;
143
wire [2:0] rm3;
144
reg [EMSB:0] xdiff3;
145
// which has greater magnitude ? Used for sign calc
146
reg a_gt_b3;
147
reg resZero3;
148
reg [FMSB+1:0] mfs3;
149
 
150
delay1 #(EMSB+1)  dxa3(.clk(clk), .ce(ce), .i(xa2), .o(xa3));
151
delay1 #(EMSB+1)  dxb3(.clk(clk), .ce(ce), .i(xb2), .o(xb3));
152
delay1 #(1) dxabInf2(.clk(clk), .ce(ce), .i(xabInf2), .o(xabInf3));
153
delay1 #(1) dxagtxb2(.clk(clk), .ce(ce), .i(xa_gt_xb2), .o(xa_gt_xb3));
154
delay2 #(1) dsa2(.clk(clk), .ce(ce), .i(sa1), .o(sa3));
155
delay2 #(1) dsb2(.clk(clk), .ce(ce), .i(sb1), .o(sb3));
156
delay2 #(1) dop2(.clk(clk), .ce(ce), .i(op1), .o(op3));
157
delay3 #(3) drm2(.clk(clk), .ce(ce), .i(rm), .o(rm3));
158
 
159
always @(posedge clk)
160
        if (ce) a_gt_b3 <= xa_gt_xb2 || var2;
161
// Find out if the result will be zero.
162
always @(posedge clk)
163
        if (ce) resZero3 <= (realOp2 & xabeq2 & mabeq2) |       anbz2;  // subtract, same magnitude,    both a,b zero
164
 
165
// Compute the difference in exponents, provides shift amount
166
always @(posedge clk)
167
        if (ce) xdiff3 <= xa_gt_xb2 ? xad2 - xbd2 : xbd2 - xad2;
168
// determine which fraction to denormalize
169
always @(posedge clk)
170
        if (ce) mfs3 <= xa_gt_xb2 ? fractb2 : fracta2;
171
 
172
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
173
// Clock edge #4
174
// Compute output exponent
175
//
176
// The output exponent is the larger of the two exponents, unless a subtract
177
// operation is in progress and the two numbers are equal, in which case the
178
// exponent should be zero.
179
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
180
reg [EMSB:0] xdif4;
181
wire [FMSB+1:0] mfs4;
182
reg [EMSB:0] xo4;        // de normalized exponent output
183
reg so4;
184
 
185
always @(posedge clk)
186
        if (ce) xo4 <= xabInf3 ? xa3 : resZero3 ? {EMSB+1{1'b0}} : xa_gt_xb3 ? xa3 : xb3;
187
 
188
// Compute output sign
189
always @(posedge clk)
190
if (ce)
191
        case ({resZero3,sa3,op3,sb3})   // synopsys full_case parallel_case
192
        4'b0000: so4 <= 0;                       // + + + = +
193
        4'b0001: so4 <= !a_gt_b3;       // + + - = sign of larger
194
        4'b0010: so4 <= !a_gt_b3;       // + - + = sign of larger
195
        4'b0011: so4 <= 0;                       // + - - = +
196
        4'b0100: so4 <= a_gt_b3;                // - + + = sign of larger
197
        4'b0101: so4 <= 1;                      // - + - = -
198
        4'b0110: so4 <= 1;                      // - - + = -
199
        4'b0111: so4 <= a_gt_b3;                // - - - = sign of larger
200
        4'b1000: so4 <= 0;                       //  A +  B, sign = +
201
        4'b1001: so4 <= rm3==3'd3;              //  A + -B, sign = + unless rounding down
202
        4'b1010: so4 <= rm3==3'd3;              //  A -  B, sign = + unless rounding down
203
        4'b1011: so4 <= 0;                       // +A - -B, sign = +
204
        4'b1100: so4 <= rm3==3'd3;              // -A +  B, sign = + unless rounding down
205
        4'b1101: so4 <= 1;                      // -A + -B, sign = -
206
        4'b1110: so4 <= 1;                      // -A - +B, sign = -
207
        4'b1111: so4 <= rm3==3'd3;              // -A - -B, sign = + unless rounding down
208
        endcase
209
 
210
always @(posedge clk)
211
if (ce) xdif4 <= xdiff3 > FMSB+3 ? FMSB+3 : xdiff3;
212
delay1 #(FMSB+2) dmsf3(.clk(clk), .ce(ce), .i(mfs3), .o(mfs4));
213
 
214
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
215
// Clock edge #5
216
// Determine the sticky bit
217
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
218
wire [EMSB:0] xdif5;
219
wire [FMSB+1:0] mfs5;
220
wire sticky, sticky5;
221
 
222
// register inputs to shifter and shift
223
delay1 #(1)      dstky4(.clk(clk), .ce(ce), .i(sticky), .o(sticky5) );
224
delay1 #(EMSB+1) dxdif4(.clk(clk), .ce(ce), .i(xdif4), .o(xdif5) );
225
delay1 #(FMSB+2) dmsf4(.clk(clk), .ce(ce), .i(mfs4), .o(mfs5));
226
 
227
generate
228
begin
229
if (FPWID+`EXTRA_BITS==128)
230
    redor128 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
231
else if (FPWID+`EXTRA_BITS==96)
232
    redor96 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
233
else if (FPWID+`EXTRA_BITS==84)
234
    redor84 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
235
else if (FPWID+`EXTRA_BITS==80)
236
    redor80 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
237
else if (FPWID+`EXTRA_BITS==64)
238
    redor64 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
239
else if (FPWID+`EXTRA_BITS==40)
240
    redor40 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
241
else if (FPWID+`EXTRA_BITS==32)
242
    redor32 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
243
end
244
endgenerate
245
 
246
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
247
// Clock edge #6
248
// Shift (denormalize)
249
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
250
reg [FMSB+3:0] md6;
251
wire xa_gt_xb6;
252
wire [FMSB+1:0] fracta6, fractb6;
253
 
254
delay3 #(1) dxagtxb5(.clk(clk), .ce(ce), .i(xa_gt_xb3), .o(xa_gt_xb6));
255
delay4 #(FMSB+2)  dfracta5(.clk(clk), .ce(ce), .i(fracta2), .o(fracta6) );
256
delay4 #(FMSB+2)  dfractb5(.clk(clk), .ce(ce), .i(fractb2), .o(fractb6) );
257
 
258
always @(posedge clk)
259
        if (ce) md6 <= ({mfs5,2'b0} >> xdif5)|sticky5;
260
 
261
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
262
// Clock edge #7
263
// Sort operands
264
// addition can generate an extra bit, subtract can't go negative
265
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
266
reg [FMSB+3:0] oa7;
267
reg [FMSB+3:0] ob7;
268
wire a_gt_b7;
269
 
270
delay4 #(1) dagtb5(.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b7));
271
 
272
always @(posedge clk)
273
        if (ce) oa7 <= xa_gt_xb6 ? {fracta6,2'b0} : md6;
274
always @(posedge clk)
275
        if (ce) ob7 <= xa_gt_xb6 ? md6 : {fractb6,2'b0};
276
 
277
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
278
// Clock edge #8
279
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
280
reg [FMSB+3:0] oaa8;
281
reg [FMSB+3:0] obb8;
282
wire [EMSB:0] xo8;
283
wire realOp8;
284
vtdl #(.WID(1)) drealop7 (.clk(clk), .ce(ce), .a(4'd5), .d(realOp2), .q(realOp8));
285
vtdl #(.WID(EMSB+1)) dxo7(.clk(clk), .ce(ce), .a(4'd3), .d(xo4), .q(xo8));
286
always @(posedge clk)
287
        if (ce) oaa8 <= a_gt_b7 ? oa7 : ob7;
288
always @(posedge clk)
289
        if (ce) obb8 <= a_gt_b7 ? ob7 : oa7;
290
 
291
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
292
// Clock edge #9
293
// perform add/subtract
294
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
295
reg [FMSB+4:0] mab9;
296
wire anbInf9;
297
wire aNan9, bNan9;
298
wire op9;
299
wire [FMSB+1:0] fracta9, fractb9;
300
wire xo9;
301
reg xinf9;
302
 
303
vtdl #(1) danbInf7(.clk(clk), .ce(ce), .a(4'd6), .d(anbInf2), .q(anbInf9));
304
vtdl #(1) danan8(.clk(clk), .ce(ce), .a(4'd7), .d(aNan1), .q(aNan9));
305
vtdl #(1) dbnan8(.clk(clk), .ce(ce), .a(4'd7), .d(bNan1), .q(bNan9));
306
vtdl #(1) dop6(.clk(clk), .ce(ce), .a(4'd5), .d(op3), .q(op9));
307
delay3 #(FMSB+2)  dfracta8(.clk(clk), .ce(ce), .i(fracta6), .o(fracta9) );
308
delay3 #(FMSB+2)  dfractb8(.clk(clk), .ce(ce), .i(fractb6), .o(fractb9) );
309
 
310
always @(posedge clk)
311
        if (ce) mab9 <= realOp8 ? oaa8 - obb8 : oaa8 + obb8;
312
always @(posedge clk)
313
        if (ce) xinf9 <= xo8 == {EMSB+1{1'b1}};
314
 
315
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
316
// Clock edge #10
317
// Final outputs
318
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
319
vtdl #(1) dso6(.clk(clk), .ce(ce), .a(4'd5), .d(so4), .q(so));
320
vtdl #(.WID(EMSB+1)) dxo6(.clk(clk), .ce(ce), .a(4'd1), .d(xo8), .q(xo));
321
 
322
always @(posedge clk)
323
if (ce)
324
        casez({anbInf9,aNan9,bNan9,xinf9})
325
        4'b1???:        mo <= {1'b0,op9,{FMSB-1{1'b0}},op9,{FMSB{1'b0}}};       // inf +/- inf - generate QNaN on subtract, inf on add
326
        4'b01??:        mo <= {1'b1,1'b1,fracta9[FMSB-1:0],{FMSB+1{1'b0}}};      // Set MSB of Nan to convert to quiet
327
        4'b001?:        mo <= {1'b1,1'b1,fractb9[FMSB-1:0],{FMSB+1{1'b0}}};
328
        4'b0001:        mo <= 1'd0;             // exponent hit infinity -> force mantissa to zero
329
        default:        mo <= {mab9,{FMSB-1{1'b0}}};    // mab has an extra lead bit and two trailing bits
330
        endcase
331
 
332
endmodule
333
 
334
module fpAddsubnr_L10(clk, ce, rm, op, a, b, o);
335
parameter FPWID = 128;
336
`include "fpSize.sv"
337
 
338
input clk;              // system clock
339
input ce;               // core clock enable
340
input [2:0] rm;  // rounding mode
341
input op;               // operation 0 = add, 1 = subtract
342
input [MSB:0] a; // operand a
343
input [MSB:0] b; // operand b
344
output [MSB:0] o;        // output
345
 
346
wire [EX:0] o1;
347
wire [MSB+3:0] fpn0;
348
 
349
fpAddsub_L10  #(FPWID) u1 (clk, ce, rm, op, a, b, o1);
350
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
351
fpRound         #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
352
 
353
endmodule

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