OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpDiv.v] - Blame information for rev 29

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 29 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch<remove>@finitron.ca
6
//       ||
7
//
8
//      fpDiv.v
9
//    - floating point divider
10
//    - parameterized FPWIDth
11
//    - IEEE 754 representation
12
//
13
//
14
// This source file is free software: you can redistribute it and/or modify 
15
// it under the terms of the GNU Lesser General Public License as published 
16
// by the Free Software Foundation, either version 3 of the License, or     
17
// (at your option) any later version.                                      
18
//                                                                          
19
// This source file is distributed in the hope that it will be useful,      
20
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
21
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
22
// GNU General Public License for more details.                             
23
//                                                                          
24
// You should have received a copy of the GNU General Public License        
25
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
26
//                                                                          
27
//      Floating Point Multiplier / Divider
28
//
29
//Properties:
30
//+-inf * +-inf = -+inf    (this is handled by exOver)
31
//+-inf * 0     = QNaN
32
//+-0 / +-0      = QNaN
33
// ============================================================================
34
 
35
`include "fpConfig.sv"
36
`include "fp_defines.v"
37
//`define GOLDSCHMIDT   1'b1
38
 
39
module fpDiv(rst, clk, clk4x, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
40
 
41
parameter FPWID = 128;
42
`include "fpSize.sv"
43
// FADD is a constant that makes the divider FPWIDth a multiple of four and includes eight extra bits.                  
44
localparam FADD = FPWID+`EXTRA_BITS==128 ? 9 :
45
                                  FPWID+`EXTRA_BITS==96 ? 9 :
46
                                  FPWID+`EXTRA_BITS==84 ? 9 :
47
                                  FPWID+`EXTRA_BITS==80 ? 9 :
48
                                  FPWID+`EXTRA_BITS==64 ? 13 :
49
                                  FPWID+`EXTRA_BITS==52 ? 9 :
50
                                  FPWID+`EXTRA_BITS==48 ? 10 :
51
                                  FPWID+`EXTRA_BITS==44 ? 9 :
52
                                  FPWID+`EXTRA_BITS==42 ? 11 :
53
                                  FPWID+`EXTRA_BITS==40 ? 8 :
54
                                  FPWID+`EXTRA_BITS==32 ? 10 :
55
                                  FPWID+`EXTRA_BITS==24 ? 9 : 11;
56
 
57
input rst;
58
input clk;
59
input clk4x;
60
input ce;
61
input ld;
62
input op;
63
input [MSB:0] a, b;
64
output [EX:0] o;
65
output done;
66
output sign_exe;
67
output overflow;
68
output underflow;
69
 
70
// registered outputs
71
reg sign_exe=0;
72
reg inf=0;
73
reg     overflow=0;
74
reg     underflow=0;
75
 
76
reg so;
77
reg [EMSB:0] xo;
78
reg [FX:0] mo;
79
assign o = {so,xo,mo};
80
 
81
// constants
82
wire [EMSB:0] infXp = {EMSB+1{1'b1}};    // infinite / NaN - all ones
83
// The following is the value for an exponent of zero, with the offset
84
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
85
wire [EMSB:0] bias = {1'b0,{EMSB{1'b1}}};        //2^0 exponent
86
// The following is a template for a quiet nan. (MSB=1)
87
wire [FMSB:0] qNaN  = {1'b1,{FMSB{1'b0}}};
88
 
89
// variables
90
wire [EMSB+2:0] ex1;     // sum of exponents
91
`ifndef GOLDSCHMIDT
92
wire [(FMSB+FADD)*2-1:0] divo;
93
`else
94
wire [(FMSB+5)*2-1:0] divo;
95
`endif
96
 
97
// Operands
98
wire sa, sb;                    // sign bit
99
wire [EMSB:0] xa, xb;    // exponent bits
100
wire [FMSB+1:0] fracta, fractb;
101
wire a_dn, b_dn;                        // a/b is denormalized
102
wire az, bz;
103
wire aInf, bInf;
104
wire aNan,bNan;
105
wire done1;
106
wire signed [7:0] lzcnt;
107
 
108
// -----------------------------------------------------------
109
// - decode the input operands
110
// - derive basic information
111
// - calculate exponent
112
// - calculate fraction
113
// -----------------------------------------------------------
114
 
115
fpDecomp #(FPWID) u1a (.i(a), .sgn(sa), .exp(xa), .fract(fracta), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );
116
fpDecomp #(FPWID) u1b (.i(b), .sgn(sb), .exp(xb), .fract(fractb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );
117
 
118
// Compute the exponent.
119
// - correct the exponent for denormalized operands
120
// - adjust the difference by the bias (add 127)
121
// - also factor in the different decimal position for division
122
`ifndef GOLDSCHMIDT
123
assign ex1 = (xa|a_dn) - (xb|b_dn) + bias + FMSB + (FADD-1) - lzcnt - 8'd1;
124
`else
125
assign ex1 = (xa|a_dn) - (xb|b_dn) + bias + FMSB - lzcnt + 8'd4;
126
`endif
127
 
128
// check for exponent underflow/overflow
129
wire under = ex1[EMSB+2];       // MSB set = negative exponent
130
wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
131
 
132
// Perform divide
133
// Divider FPWIDth must be a multiple of four
134
`ifndef GOLDSCHMIDT
135
fpdivr16 #(FMSB+FADD) u2 (.clk(clk), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
136
//fpdivr2 #(FMSB+FADD) u2 (.clk4x(clk4x), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
137
wire [(FMSB+FADD)*2-1:0] divo1 = divo[(FMSB+FADD)*2-1:0] << (lzcnt-2);
138
`else
139
DivGoldschmidt #(.FPWID(FMSB+6),.WHOLE(1),.POINTS(FMSB+5))
140
        u2 (.rst(rst), .clk(clk), .ld(ld), .a({fracta,4'b0}), .b({fractb,4'b0}), .q(divo), .done(done1), .lzcnt(lzcnt));
141
wire [(FMSB+6)*2+1:0] divo1 =
142
        lzcnt > 8'd5 ? divo << (lzcnt-8'd6) :
143
        divo >> (8'd6-lzcnt);
144
        ;
145
`endif
146
delay1 #(1) u3 (.clk(clk), .ce(ce), .i(done1), .o(done));
147
 
148
 
149
// determine when a NaN is output
150
wire qNaNOut = (az&bz)|(aInf&bInf);
151
 
152
always @(posedge clk)
153
// Simulation likes to see these values reset to zero on reset. Otherwise the
154
// values propagate in sim as X's.
155
if (rst) begin
156
        xo <= 1'd0;
157
        mo <= 1'd0;
158
        so <= 1'd0;
159
        sign_exe <= 1'd0;
160
        overflow <= 1'd0;
161
        underflow <= 1'd0;
162
end
163
else if (ce) begin
164
                if (done1) begin
165
                        casez({qNaNOut|aNan|bNan,bInf,bz,over,under})
166
                        5'b1????:               xo <= infXp;    // NaN exponent value
167
                        5'b01???:               xo <= 1'd0;             // divide by inf
168
                        5'b001??:               xo <= infXp;    // divide by zero
169
                        5'b0001?:               xo <= infXp;    // overflow
170
                        5'b00001:               xo <= 1'd0;             // underflow
171
                        default:                xo <= ex1;      // normal or underflow: passthru neg. exp. for normalization
172
                        endcase
173
 
174
                        casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
175
                        8'b1???????:  mo <= {1'b1,1'b1,a[FMSB-1:0],{FMSB+1{1'b0}}};
176
                        8'b01??????:  mo <= {1'b1,1'b1,b[FMSB-1:0],{FMSB+1{1'b0}}};
177
                        8'b001?????:    mo <= {1'b1,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};
178
                        8'b0001????:    mo <= 1'd0;     // div by inf
179
                        8'b00001???:    mo <= 1'd0;     // div by zero
180
                        8'b000001??:    mo <= 1'd0;     // Inf exponent
181
                        8'b0000001?:    mo <= {1'b1,qNaN|`QINFDIV,{FMSB+1{1'b0}}};      // infinity / infinity
182
                        8'b00000001:    mo <= {1'b1,qNaN|`QZEROZERO,{FMSB+1{1'b0}}};    // zero / zero
183
`ifndef GOLDSCHMIDT
184
                        default:                mo <= divo1[(FMSB+FADD)*2-1:(FADD-2)*2-2];      // plain div
185
`else
186
                        default:                mo <= divo1[(FMSB+6)*2+1:2];    // plain div
187
`endif
188
                        endcase
189
 
190
                        so              <= sa ^ sb;
191
                        sign_exe        <= sa & sb;
192
                        overflow        <= over;
193
                        underflow       <= under;
194
                end
195
        end
196
 
197
endmodule
198
 
199
module fpDivnr(rst, clk, clk4x, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
200
parameter FPWID=32;
201
`include "fpSize.sv"
202
 
203
input rst;
204
input clk;
205
input clk4x;
206
input ce;
207
input ld;
208
input op;
209
input  [MSB:0] a, b;
210
output [MSB:0] o;
211
input [2:0] rm;
212
output sign_exe;
213
output done;
214
output inf;
215
output overflow;
216
output underflow;
217
 
218
wire [EX:0] o1;
219
wire sign_exe1, inf1, overflow1, underflow1;
220
wire [MSB+3:0] fpn0;
221
wire done1;
222
 
223
fpDiv       #(FPWID) u1 (rst, clk, clk4x, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
224
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under(underflow1), .i(o1), .o(fpn0) );
225
fpRound                 #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
226
delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
227
delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
228
delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
229
delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
230
delay2            #(1)   u8(.clk(clk), .ce(ce), .i(done1), .o(done));
231
endmodule
232
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.