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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpDivide.sv] - Blame information for rev 84

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      fpDivide.sv
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//    - floating point divider
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//    - parameterized width
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//    - IEEE 754 representation
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//      Floating Point Divider
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//
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//Properties:
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//+-inf * +-inf = -+inf    (this is handled by exOver)
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//+-inf * 0     = QNaN
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//+-0 / +-0      = QNaN
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// ============================================================================
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import fp::*;
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//`define GOLDSCHMIDT   1'b1
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module fpDivide(rst, clk, clk4x, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
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// FADD is a constant that makes the divider width a multiple of four and includes eight extra bits.
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localparam FADD = FPWID==128 ? 9 :
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                                  FPWID==96 ? 9 :
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                                  FPWID==84 ? 9 :
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                                  FPWID==80 ? 9 :
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                                  FPWID==64 ? 13 :
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                                  FPWID==52 ? 9 :
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                                  FPWID==48 ? 10 :
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                                  FPWID==44 ? 9 :
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                                  FPWID==42 ? 11 :
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                                  FPWID==40 ? 8 :
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                                  FPWID==32 ? 10 :
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                                  FPWID==24 ? 9 : 11;
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input rst;
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input clk;
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input clk4x;
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input ce;
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input ld;
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input op;
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input [MSB:0] a, b;
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output [EX:0] o;
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output done;
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output sign_exe;
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output overflow;
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output underflow;
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// registered outputs
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reg sign_exe=0;
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reg inf=0;
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reg     overflow=0;
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reg     underflow=0;
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reg so;
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reg [EMSB:0] xo;
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reg [FX:0] mo;
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assign o = {so,xo,mo};
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// constants
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wire [EMSB:0] infXp = {EMSB+1{1'b1}};   // infinite / NaN - all ones
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// The following is the value for an exponent of zero, with the offset
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// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
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wire [EMSB:0] bias = {1'b0,{EMSB{1'b1}}};       //2^0 exponent
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// The following is a template for a quiet nan. (MSB=1)
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wire [FMSB:0] qNaN  = {1'b1,{FMSB{1'b0}}};
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// variables
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wire [EMSB+2:0] ex1;    // sum of exponents
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`ifndef GOLDSCHMIDT
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wire [(FMSB+FADD)*2-1:0] divo;
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`else
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wire [(FMSB+5)*2-1:0] divo;
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`endif
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// Operands
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wire sa, sb;                    // sign bit
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wire [EMSB:0] xa, xb;   // exponent bits
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wire [FMSB+1:0] fracta, fractb;
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wire a_dn, b_dn;                        // a/b is denormalized
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wire az, bz;
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wire aInf, bInf;
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wire aNan,bNan;
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wire done1;
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wire signed [7:0] lzcnt;
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// -----------------------------------------------------------
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// - decode the input operands
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// - derive basic information
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// - calculate exponent
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// - calculate fraction
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// -----------------------------------------------------------
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fpDecomp u1a (.i(a), .sgn(sa), .exp(xa), .fract(fracta), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );
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fpDecomp u1b (.i(b), .sgn(sb), .exp(xb), .fract(fractb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );
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// Compute the exponent.
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// - correct the exponent for denormalized operands
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// - adjust the difference by the bias (add 127)
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// - also factor in the different decimal position for division
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`ifndef GOLDSCHMIDT
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assign ex1 = (xa|a_dn) - (xb|b_dn) + bias + FMSB + (FADD-1) - lzcnt - 8'd1;
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`else
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assign ex1 = (xa|a_dn) - (xb|b_dn) + bias + FMSB - lzcnt + 8'd4;
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`endif
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// check for exponent underflow/overflow
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wire under = ex1[EMSB+2];       // MSB set = negative exponent
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wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
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// Perform divide
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// Divider width must be a multiple of four
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`ifndef GOLDSCHMIDT
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fpdivr16 #(FMSB+FADD) u2 (.clk(clk), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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//fpdivr2 #(FMSB+FADD) u2 (.clk4x(clk4x), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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wire [(FMSB+FADD)*2-1:0] divo1 = divo[(FMSB+FADD)*2-1:0] << (lzcnt-2);
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`else
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DivGoldschmidt #(.WID(FMSB+6),.WHOLE(1),.POINTS(FMSB+5))
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        u2 (.rst(rst), .clk(clk), .ld(ld), .a({fracta,4'b0}), .b({fractb,4'b0}), .q(divo), .done(done1), .lzcnt(lzcnt));
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wire [(FMSB+6)*2+1:0] divo1 =
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        lzcnt > 8'd5 ? divo << (lzcnt-8'd6) :
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        divo >> (8'd6-lzcnt);
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        ;
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`endif
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delay1 #(1) u3 (.clk(clk), .ce(ce), .i(done1), .o(done));
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// determine when a NaN is output
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wire qNaNOut = (az&bz)|(aInf&bInf);
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always @(posedge clk)
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// Simulation likes to see these values reset to zero on reset. Otherwise the
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// values propagate in sim as X's.
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if (rst) begin
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        xo <= 1'd0;
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        mo <= 1'd0;
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        so <= 1'd0;
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        sign_exe <= 1'd0;
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        overflow <= 1'd0;
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        underflow <= 1'd0;
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end
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else if (ce) begin
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                if (done1) begin
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                        casez({qNaNOut|aNan|bNan,bInf,bz,over,under})
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                        5'b1????:               xo <= infXp;    // NaN exponent value
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                        5'b01???:               xo <= 1'd0;             // divide by inf
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                        5'b001??:               xo <= infXp;    // divide by zero
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                        5'b0001?:               xo <= infXp;    // overflow
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                        5'b00001:               xo <= 1'd0;             // underflow
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                        default:                xo <= ex1;      // normal or underflow: passthru neg. exp. for normalization
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                        endcase
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                        casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
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                        8'b1???????:    mo <= {1'b1,a[FMSB:0],{FMSB+1{1'b0}}};
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                        8'b01??????:    mo <= {1'b1,b[FMSB:0],{FMSB+1{1'b0}}};
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                        8'b001?????:    mo <= {1'b1,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};
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                        8'b0001????:    mo <= 1'd0;     // div by inf
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                        8'b00001???:    mo <= 1'd0;     // div by zero
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                        8'b000001??:    mo <= 1'd0;     // Inf exponent
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                        8'b0000001?:    mo <= {1'b1,qNaN|`QINFDIV,{FMSB+1{1'b0}}};      // infinity / infinity
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                        8'b00000001:    mo <= {1'b1,qNaN|`QZEROZERO,{FMSB+1{1'b0}}};    // zero / zero
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`ifndef GOLDSCHMIDT
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                        default:                mo <= divo1[(FMSB+FADD)*2-1:(FADD-2)*2-2];      // plain div
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`else
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                        default:                mo <= divo1[(FMSB+6)*2+1:2];    // plain div
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`endif
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                        endcase
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                        so              <= sa ^ sb;
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                        sign_exe        <= sa & sb;
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                        overflow        <= over;
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                        underflow       <= under;
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                end
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        end
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endmodule
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module fpDividenr(rst, clk, clk4x, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
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input rst;
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input clk;
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input clk4x;
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input ce;
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input ld;
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input op;
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input  [MSB:0] a, b;
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output [MSB:0] o;
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input [2:0] rm;
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output sign_exe;
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output done;
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output inf;
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output overflow;
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output underflow;
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wire [EX:0] o1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire [MSB+3:0] fpn0;
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wire done1;
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fpDivide    #(FPWID) u1 (rst, clk, clk4x, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
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fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
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fpRound     #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
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delay2            #(1)   u8(.clk(clk), .ce(ce), .i(done1), .o(done));
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endmodule
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