OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpFMA.sv] - Blame information for rev 49

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 48 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2019-2020  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch@finitron.ca
6
//       ||
7
//
8
//      fpFMA.sv
9
//              - floating point fused multiplier + adder
10
//              - can issue every clock cycle
11
//              - parameterized FPWIDth
12
//              - IEEE 754 representation
13
//
14
//
15
// This source file is free software: you can redistribute it and/or modify
16
// it under the terms of the GNU Lesser General Public License as published
17
// by the Free Software Foundation, either version 3 of the License, or
18
// (at your option) any later version.
19
//
20
// This source file is distributed in the hope that it will be useful,
21
// but WITHOUT ANY WARRANTY; without even the implied warranty of
22
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23
// GNU General Public License for more details.
24
//
25
// You should have received a copy of the GNU General Public License
26
// along with this program.  If not, see .
27
//
28
// ============================================================================
29
 
30
import fp::*;
31
 
32
module fpFMA (clk, ce, op, rm, a, b, c, o, under, over, inf, zero);
33
input clk;
34
input ce;
35
input op;               // operation 0 = add, 1 = subtract
36
input [2:0] rm;
37
input  [MSB:0] a, b, c;
38
output [EX:0] o;
39
output under;
40
output over;
41
output inf;
42
output zero;
43
 
44
// constants
45
wire [EMSB:0] infXp = {EMSB+1{1'b1}};   // infinite / NaN - all ones
46
// The following is the value for an exponent of zero, with the offset
47
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
48
wire [EMSB:0] bias = {1'b0,{EMSB{1'b1}}};       //2^0 exponent
49
// The following is a template for a quiet nan. (MSB=1)
50
wire [FMSB:0] qNaN  = {1'b1,{FMSB{1'b0}}};
51
 
52
// -----------------------------------------------------------
53
// Clock #1
54
// - decode the input operands
55
// - derive basic information
56
// -----------------------------------------------------------
57
 
58
wire sa1, sb1, sc1;                     // sign bit
59
wire [EMSB:0] xa1, xb1, xc1;    // exponent bits
60
wire [FMSB+1:0] fracta1, fractb1, fractc1;      // includes unhidden bit
61
wire a_dn1, b_dn1, c_dn1;                       // a/b is denormalized
62
wire aNan1, bNan1, cNan1;
63
wire az1, bz1, cz1;
64
wire aInf1, bInf1, cInf1;
65
reg op1;
66
 
67
fpDecompReg u1a (.clk(clk), .ce(ce), .i(a), .sgn(sa1), .exp(xa1), .fract(fracta1), .xz(a_dn1), .vz(az1), .inf(aInf1), .nan(aNan1) );
68
fpDecompReg u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb1), .exp(xb1), .fract(fractb1), .xz(b_dn1), .vz(bz1), .inf(bInf1), .nan(bNan1) );
69
fpDecompReg u1c (.clk(clk), .ce(ce), .i(c), .sgn(sc1), .exp(xc1), .fract(fractc1), .xz(c_dn1), .vz(cz1), .inf(cInf1), .nan(cNan1) );
70
 
71
always @(posedge clk)
72
        if (ce) op1 <= op;
73
 
74
// -----------------------------------------------------------
75
// Clock #2
76
// Compute the sum of the exponents.
77
// correct the exponent for denormalized operands
78
// adjust the sum by the exponent offset (subtract 127)
79
// mul: ex1 = xa + xb,  result should always be < 1ffh
80
// Form partial products (clocks 2 to 5)
81
// -----------------------------------------------------------
82
 
83
reg abz2;
84
reg [EMSB+2:0] ex2;
85
reg [EMSB:0] xc2;
86
reg realOp2;
87
reg xcInf2;
88
 
89
always @(posedge clk)
90
        if (ce) abz2 <= az1|bz1;
91
always @(posedge clk)
92
        if (ce) ex2 <= (xa1|a_dn1) + (xb1|b_dn1) - bias;
93
always @(posedge clk)
94
        if (ce) xc2 <= (xc1|c_dn1);
95
always @(posedge clk)
96
        if (ce) xcInf2 = &xc1;
97
 
98
// Figure out which operation is really needed an add or
99
// subtract ?
100
// If the signs are the same, use the orignal op,
101
// otherwise flip the operation
102
//  a +  b = add,+
103
//  a + -b = sub, so of larger
104
// -a +  b = sub, so of larger
105
// -a + -b = add,-
106
//  a -  b = sub, so of larger
107
//  a - -b = add,+
108
// -a -  b = add,-
109
// -a - -b = sub, so of larger
110
always @(posedge clk)
111
        if (ce) realOp2 <= op1 ^ (sa1 ^ sb1) ^ sc1;
112
 
113
 
114
reg [FX:0] fract5;
115
generate
116
if (FPWID==84) begin
117
reg [33:0] p00,p01,p02,p03;
118
reg [33:0] p10,p11,p12,p13;
119
reg [33:0] p20,p21,p22,p23;
120
reg [33:0] p30,p31,p32,p33;
121
reg [135:0] fract3a;
122
reg [135:0] fract3b;
123
reg [135:0] fract3c;
124
reg [135:0] fract3d;
125
reg [135:0] fract4a;
126
reg [135:0] fract4b;
127
 
128
        always @(posedge clk)
129
        if (ce) begin
130
                p00 <= fracta1[16: 0] * fractb1[16: 0];
131
                p01 <= fracta1[33:17] * fractb1[16: 0];
132
                p02 <= fracta1[50:34] * fractb1[16: 0];
133
                p03 <= fracta1[67:51] * fractb1[16: 0];
134
 
135
                p10 <= fracta1[16: 0] * fractb1[33:17];
136
                p11 <= fracta1[33:17] * fractb1[33:17];
137
                p12 <= fracta1[50:34] * fractb1[33:17];
138
                p13 <= fracta1[67:51] * fractb1[33:17];
139
 
140
                p20 <= fracta1[16: 0] * fractb1[50:34];
141
                p21 <= fracta1[33:17] * fractb1[50:34];
142
                p22 <= fracta1[50:34] * fractb1[50:34];
143
                p23 <= fracta1[67:51] * fractb1[50:34];
144
 
145
                p30 <= fracta1[15: 0] * fractb1[67:51];
146
                p31 <= fracta1[31:16] * fractb1[67:51];
147
                p32 <= fracta1[47:32] * fractb1[67:51];
148
                p33 <= fracta1[63:48] * fractb1[67:51];
149
        end
150
        always @(posedge clk)
151
        if (ce) begin
152
                fract3a <= {p33,p31,p20,p00};
153
                fract3b <= {p32,p12,p10,17'b0} + {p23,p03,p01,17'b0};
154
                fract3c <= {p22,p11,34'b0} + {p13,p02,34'b0};
155
                fract3d <= {p12,51'b0} + {p03,51'b0};
156
        end
157
        always @(posedge clk)
158
        if (ce) begin
159
                fract4a <= fract3a + fract3b;
160
                fract4b <= fract3c + fract3d;
161
        end
162
        always @(posedge clk)
163
        if (ce) begin
164
                fract5 <= fract4a + fract4b;
165
        end
166
end
167
else if (FPWID==80) begin
168
reg [31:0] p00,p01,p02,p03;
169
reg [31:0] p10,p11,p12,p13;
170
reg [31:0] p20,p21,p22,p23;
171
reg [31:0] p30,p31,p32,p33;
172
reg [127:0] fract3a;
173
reg [127:0] fract3b;
174
reg [127:0] fract3c;
175
reg [127:0] fract3d;
176
reg [127:0] fract4a;
177
reg [127:0] fract4b;
178
 
179
        always @(posedge clk)
180
        if (ce) begin
181
                p00 <= fracta1[15: 0] * fractb1[15: 0];
182
                p01 <= fracta1[31:16] * fractb1[15: 0];
183
                p02 <= fracta1[47:32] * fractb1[15: 0];
184
                p03 <= fracta1[63:48] * fractb1[15: 0];
185
 
186
                p10 <= fracta1[15: 0] * fractb1[31:16];
187
                p11 <= fracta1[31:16] * fractb1[31:16];
188
                p12 <= fracta1[47:32] * fractb1[31:16];
189
                p13 <= fracta1[63:48] * fractb1[31:16];
190
 
191
                p20 <= fracta1[15: 0] * fractb1[47:32];
192
                p21 <= fracta1[31:16] * fractb1[47:32];
193
                p22 <= fracta1[47:32] * fractb1[47:32];
194
                p23 <= fracta1[63:48] * fractb1[47:32];
195
 
196
                p30 <= fracta1[15: 0] * fractb1[63:48];
197
                p31 <= fracta1[31:16] * fractb1[63:48];
198
                p32 <= fracta1[47:32] * fractb1[63:48];
199
                p33 <= fracta1[63:48] * fractb1[63:48];
200
        end
201
        always @(posedge clk)
202
        if (ce) begin
203
                fract3a <= {p33,p31,p20,p00};
204
                fract3b <= {p32,p12,p10,16'b0} + {p23,p03,p01,16'b0};
205
                fract3c <= {p22,p11,32'b0} + {p13,p02,32'b0};
206
                fract3d <= {p12,48'b0} + {p03,48'b0};
207
        end
208
        always @(posedge clk)
209
        if (ce) begin
210
                fract4a <= fract3a + fract3b;
211
                fract4b <= fract3c + fract3d;
212
        end
213
        always @(posedge clk)
214
        if (ce) begin
215
                fract5 <= fract4a + fract4b;
216
        end
217
end
218
else if (FPWID==64) begin
219
reg [35:0] p00,p01,p02;
220
reg [35:0] p10,p11,p12;
221
reg [35:0] p20,p21,p22;
222
reg [71:0] fract3a;
223
reg [89:0] fract3b;
224
reg [107:0] fract3c;
225
reg [108:0] fract4a;
226
reg [108:0] fract4b;
227
 
228
        always @(posedge clk)
229
        if (ce) begin
230
                p00 <= fracta1[17: 0] * fractb1[17: 0];
231
                p01 <= fracta1[35:18] * fractb1[17: 0];
232
                p02 <= fracta1[52:36] * fractb1[17: 0];
233
                p10 <= fracta1[17: 0] * fractb1[35:18];
234
                p11 <= fracta1[35:18] * fractb1[35:18];
235
                p12 <= fracta1[52:36] * fractb1[35:18];
236
                p20 <= fracta1[17: 0] * fractb1[52:36];
237
                p21 <= fracta1[35:18] * fractb1[52:36];
238
                p22 <= fracta1[52:36] * fractb1[52:36];
239
        end
240
        always @(posedge clk)
241
        if (ce) begin
242
                fract3a <= {p02,p00};
243
                fract3b <= {p21,p10,18'b0} + {p12,p01,18'b0};
244
                fract3c <= {p22,p20,36'b0} + {p11,36'b0};
245
        end
246
        always @(posedge clk)
247
        if (ce) begin
248
                fract4a <= fract3a + fract3b;
249
                fract4b <= fract3c;
250
        end
251
        always @(posedge clk)
252
        if (ce) begin
253
                fract5 <= fract4a + fract4b;
254
        end
255
end
256
else if (FPWID==40) begin
257
reg [27:0] p00,p01,p02;
258
reg [27:0] p10,p11,p12;
259
reg [27:0] p20,p21,p22;
260
reg [79:0] fract3a;
261
reg [79:0] fract3b;
262
reg [79:0] fract3c;
263
reg [79:0] fract4a;
264
reg [79:0] fract4b;
265
        always @(posedge clk)
266
        if (ce) begin
267
                p00 <= fracta1[13: 0] * fractb1[13: 0];
268
                p01 <= fracta1[27:14] * fractb1[13: 0];
269
                p02 <= fracta1[39:28] * fractb1[13: 0];
270
                p10 <= fracta1[13: 0] * fractb1[27:14];
271
                p11 <= fracta1[27:14] * fractb1[27:14];
272
                p12 <= fracta1[39:28] * fractb1[27:14];
273
                p20 <= fracta1[13: 0] * fractb1[39:28];
274
                p21 <= fracta1[27:14] * fractb1[39:28];
275
                p22 <= fracta1[39:28] * fractb1[39:28];
276
        end
277
        always @(posedge clk)
278
        if (ce) begin
279
                fract3a <= {p02,p00};
280
                fract3b <= {p21,p10,18'b0} + {p12,p01,18'b0};
281
                fract3c <= {p22,p20,36'b0} + {p11,36'b0};
282
        end
283
        always @(posedge clk)
284
        if (ce) begin
285
                fract4a <= fract3a + fract3b;
286
                fract4b <= fract3c;
287
        end
288
        always @(posedge clk)
289
        if (ce) begin
290
                fract5 <= fract4a + fract4b;
291
        end
292
end
293
else if (FPWID==32) begin
294
reg [23:0] p00,p01,p02;
295
reg [23:0] p10,p11,p12;
296
reg [23:0] p20,p21,p22;
297
reg [63:0] fract3a;
298
reg [63:0] fract3b;
299
reg [63:0] fract4;
300
 
301
        always @(posedge clk)
302
        if (ce) begin
303
                p00 <= fracta1[11: 0] * fractb1[11: 0];
304
                p01 <= fracta1[23:12] * fractb1[11: 0];
305
                p10 <= fracta1[11: 0] * fractb1[23:12];
306
                p11 <= fracta1[23:12] * fractb1[23:12];
307
        end
308
        always @(posedge clk)
309
        if (ce) begin
310
                fract3a <= {p11,p00};
311
                fract3b <= {p01,12'b0} + {p10,12'b0};
312
        end
313
        always @(posedge clk)
314
        if (ce) begin
315
                fract4 <= fract3a + fract3b;
316
        end
317
        always @(posedge clk)
318
        if (ce) begin
319
                fract5 <= fract4;
320
        end
321
end
322
else begin
323
reg [FX:0] p00;
324
reg [FX:0] fract3;
325
reg [FX:0] fract4;
326
        always @(posedge clk)
327
    if (ce) begin
328
        p00 <= fracta1 * fractb1;
329
    end
330
        always @(posedge clk)
331
    if (ce)
332
        fract3 <= p00;
333
        always @(posedge clk)
334
    if (ce)
335
        fract4 <= fract3;
336
        always @(posedge clk)
337
    if (ce)
338
        fract5 <= fract4;
339
end
340
endgenerate
341
 
342
// -----------------------------------------------------------
343
// Clock #3
344
// Select zero exponent
345
// -----------------------------------------------------------
346
 
347
reg [EMSB+2:0] ex3;
348
reg [EMSB:0] xc3;
349
always @(posedge clk)
350
        if (ce) ex3 <= abz2 ? 1'd0 : ex2;
351
always @(posedge clk)
352
        if (ce) xc3 <= xc2;
353
 
354
// -----------------------------------------------------------
355
// Clock #4
356
// Generate partial products.
357
// -----------------------------------------------------------
358
 
359
reg [EMSB+2:0] ex4;
360
reg [EMSB:0] xc4;
361
 
362
always @(posedge clk)
363
        if (ce) ex4 <= ex3;
364
always @(posedge clk)
365
        if (ce) xc4 <= xc3;
366
 
367
// -----------------------------------------------------------
368
// Clock #5
369
// Sum partial products (above)
370
// compute multiplier overflow and underflow
371
// -----------------------------------------------------------
372
 
373
// Status
374
reg under5;
375
reg over5;
376
reg [EMSB+2:0] ex5;
377
reg [EMSB:0] xc5;
378
wire aInf5, bInf5;
379
wire aNan5, bNan5;
380
wire qNaNOut5;
381
 
382
always @(posedge clk)
383
        if (ce) under5 <= ex4[EMSB+2];
384
always @(posedge clk)
385
        if (ce) over5 <= (&ex4[EMSB:0] | ex4[EMSB+1]) & !ex4[EMSB+2];
386
always @(posedge clk)
387
        if (ce) ex5 <= ex4;
388
always @(posedge clk)
389
        if (ce) xc5 <= xc4;
390
 
391
delay4 u2a (.clk(clk), .ce(ce), .i(aInf1), .o(aInf5) );
392
delay4 u2b (.clk(clk), .ce(ce), .i(bInf1), .o(bInf5) );
393
 
394
// determine when a NaN is output
395
wire [MSB:0] a5,b5;
396
delay4 u5 (.clk(clk), .ce(ce), .i((aInf1&bz1)|(bInf1&az1)), .o(qNaNOut5) );
397
delay4 u14 (.clk(clk), .ce(ce), .i(aNan1), .o(aNan5) );
398
delay4 u15 (.clk(clk), .ce(ce), .i(bNan1), .o(bNan5) );
399
delay5 #(MSB+1) u16 (.clk(clk), .ce(ce), .i(a), .o(a5) );
400
delay5 #(MSB+1) u17 (.clk(clk), .ce(ce), .i(b), .o(b5) );
401
 
402
// -----------------------------------------------------------
403
// Clock #6
404
// - figure multiplier mantissa output
405
// - figure multiplier exponent output
406
// - correct xponent and mantissa for exceptional conditions
407
// -----------------------------------------------------------
408
 
409
reg [FX:0] mo6;
410
reg [EMSB+2:0] ex6;
411
reg [EMSB:0] xc6;
412
wire [FMSB+1:0] fractc6;
413
vtdl #(FMSB+2) u61 (.clk(clk), .ce(ce), .a(4'd4), .d(fractc1), .q(fractc6) );
414
delay1 u62 (.clk(clk), .ce(ce), .i(under5), .o(under6));
415
 
416
always @(posedge clk)
417
        if (ce) xc6 <= xc5;
418
 
419
always @(posedge clk)
420
        if (ce)
421
                casez({aNan5,bNan5,qNaNOut5,aInf5,bInf5,over5})
422
                6'b1?????:  mo6 <= {1'b1,1'b1,a5[FMSB-1:0],{FMSB+1{1'b0}}};
423
    6'b01????:  mo6 <= {1'b1,1'b1,b5[FMSB-1:0],{FMSB+1{1'b0}}};
424
                6'b001???:      mo6 <= {1'b1,qNaN|3'd4,{FMSB+1{1'b0}}}; // multiply inf * zero
425
                6'b0001??:      mo6 <= 0;       // mul inf's
426
                6'b00001?:      mo6 <= 0;       // mul inf's
427
                6'b000001:      mo6 <= 0;       // mul overflow
428
                default:        mo6 <= fract5;
429
                endcase
430
 
431
always @(posedge clk)
432
        if (ce)
433
                casez({qNaNOut5|aNan5|bNan5,aInf5,bInf5,over5,under5})
434
                5'b1????:       ex6 <= infXp;   // qNaN - infinity * zero
435
                5'b01???:       ex6 <= infXp;   // 'a' infinite
436
                5'b001??:       ex6 <= infXp;   // 'b' infinite
437
                5'b0001?:       ex6 <= infXp;   // result overflow
438
                5'b00001:       ex6 <= ex5;             //0;            // underflow
439
                default:        ex6 <= ex5;             // situation normal
440
                endcase
441
 
442
// -----------------------------------------------------------
443
// Clock #7
444
// - prep for addition, determine greater operand
445
// -----------------------------------------------------------
446
reg ex_gt_xc7;
447
reg xeq7;
448
reg ma_gt_mc7;
449
reg meq7;
450
wire az7, bz7, cz7;
451
wire realOp7;
452
 
453
// which has greater magnitude ? Used for sign calc
454
always @(posedge clk)
455
        if (ce) ex_gt_xc7 <= $signed(ex6) > $signed({2'b0,xc6});
456
always @(posedge clk)
457
        if (ce) xeq7 <= (ex6=={2'b0,xc6});
458
always @(posedge clk)
459
        if (ce) ma_gt_mc7 <= mo6 > {fractc6,{FMSB+1{1'b0}}};
460
always @(posedge clk)
461
        if (ce) meq7 <= mo6 == {fractc6,{FMSB+1{1'b0}}};
462
vtdl #(1) u71 (.clk(clk), .ce(ce), .a(4'd5), .d(az1), .q(az7));
463
vtdl #(1) u72 (.clk(clk), .ce(ce), .a(4'd5), .d(bz1), .q(bz7));
464
vtdl #(1) u73 (.clk(clk), .ce(ce), .a(4'd5), .d(cz1), .q(cz7));
465
vtdl #(1) u74 (.clk(clk), .ce(ce), .a(4'd4), .d(realOp2), .q(realOp7));
466
 
467
// -----------------------------------------------------------
468
// Clock #8
469
// - prep for addition, determine greater operand
470
// - determine if result will be zero
471
// -----------------------------------------------------------
472
 
473
reg a_gt_b8;
474
reg resZero8;
475
reg ex_gt_xc8;
476
wire [EMSB+2:0] ex8;
477
wire [EMSB:0] xc8;
478
wire xcInf8;
479
wire [2:0] rm8;
480
wire op8;
481
wire sa8, sc8;
482
 
483
delay2 #(EMSB+3) u81 (.clk(clk), .ce(ce), .i(ex6), .o(ex8));
484
delay2 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xc6), .o(xc8));
485
vtdl #(1) u83 (.clk(clk), .ce(ce), .a(4'd5), .d(xcInf2), .q(xcInf8));
486
vtdl #(3) u84 (.clk(clk), .ce(ce), .a(4'd7), .d(rm), .q(rm8));
487
vtdl #(1) u85 (.clk(clk), .ce(ce), .a(4'd6), .d(op1), .q(op8));
488
vtdl #(1) u86 (.clk(clk), .ce(ce), .a(4'd6), .d(sa1 ^ sb1), .q(sa8));
489
vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd6), .d(sc1), .q(sc8));
490
 
491
always @(posedge clk)
492
        if (ce) ex_gt_xc8 <= ex_gt_xc7;
493
always @(posedge clk)
494
        if (ce)
495
                a_gt_b8 <= ex_gt_xc7 || (xeq7 && ma_gt_mc7);
496
 
497
// Find out if the result will be zero.
498
always @(posedge clk)
499
        if (ce)
500
                resZero8 <= (realOp7 & xeq7 & meq7) ||  // subtract, same magnitude
501
                           ((az7 | bz7) & cz7);               // a or b zero and c zero
502
 
503
// -----------------------------------------------------------
504
// CLock #9
505
// Compute output exponent and sign
506
//
507
// The output exponent is the larger of the two exponents,
508
// unless a subtract operation is in progress and the two
509
// numbers are equal, in which case the exponent should be
510
// zero.
511
// -----------------------------------------------------------
512
 
513
reg so9;
514
reg [EMSB+2:0] ex9;
515
reg [EMSB+2:0] ex9a;
516
reg ex_gt_xc9;
517
reg [EMSB:0] xc9;
518
reg a_gt_c9;
519
wire [FX:0] mo9;
520
wire [FMSB+1:0] fractc9;
521
wire under9;
522
wire xeq9;
523
 
524
always @(posedge clk)
525
        if (ce) ex_gt_xc9 <= ex_gt_xc8;
526
always @(posedge clk)
527
        if (ce) a_gt_c9 <= a_gt_b8;
528
always @(posedge clk)
529
        if (ce) xc9 <= xc8;
530
always @(posedge clk)
531
        if (ce) ex9a <= ex8;
532
 
533
delay3 #(FX+1) u93 (.clk(clk), .ce(ce), .i(mo6), .o(mo9));
534
delay3 #(FMSB+2) u94 (.clk(clk), .ce(ce), .i(fractc6), .o(fractc9));
535
delay3 u95 (.clk(clk), .ce(ce), .i(under6), .o(under9));
536
delay2 u96 (.clk(clk), .ce(ce), .i(xeq7), .o(xeq9));
537
 
538
always @(posedge clk)
539
        if (ce) ex9 <= resZero8 ? 1'd0 : ex_gt_xc8 ? ex8 : {2'b0,xc8};
540
 
541
// Compute output sign
542
always @(posedge clk)
543
        if (ce)
544
        case ({resZero8,sa8,op8,sc8})   // synopsys full_case parallel_case
545
        4'b0000: so9 <= 0;                      // + + + = +
546
        4'b0001: so9 <= !a_gt_b8;       // + + - = sign of larger
547
        4'b0010: so9 <= !a_gt_b8;       // + - + = sign of larger
548
        4'b0011: so9 <= 0;                      // + - - = +
549
        4'b0100: so9 <= a_gt_b8;                // - + + = sign of larger
550
        4'b0101: so9 <= 1;                      // - + - = -
551
        4'b0110: so9 <= 1;                      // - - + = -
552
        4'b0111: so9 <= a_gt_b8;                // - - - = sign of larger
553
        4'b1000: so9 <= 0;                      //  A +  B, sign = +
554
        4'b1001: so9 <= rm8==3;         //  A + -B, sign = + unless rounding down
555
        4'b1010: so9 <= rm8==3;         //  A -  B, sign = + unless rounding down
556
        4'b1011: so9 <= 0;                      // +A - -B, sign = +
557
        4'b1100: so9 <= rm8==3;         // -A +  B, sign = + unless rounding down
558
        4'b1101: so9 <= 1;                      // -A + -B, sign = -
559
        4'b1110: so9 <= 1;                      // -A - +B, sign = -
560
        4'b1111: so9 <= rm8==3;         // -A - -B, sign = + unless rounding down
561
        endcase
562
 
563
// -----------------------------------------------------------
564
// Clock #10
565
// Compute the difference in exponents, provides shift amount
566
// Note that ex9a will be negative for an underflow condition
567
// so it's added rather than subtracted from xc9 as -(-num)
568
// is the same as an add. The underflow is tracked rather than
569
// using extra bits in the exponent.
570
// -----------------------------------------------------------
571
reg [EMSB+2:0] xdiff10;
572
reg [FX:0] mfs;
573
reg ops10;
574
 
575
// If the multiplier exponent was negative (underflowed) then
576
// the mantissa needs to be shifted right even more (until
577
// the exponent is zero. The total shift would be xc9-0-
578
// amount underflows which is xc9 + -ex9a.
579
 
580
always @(posedge clk)
581
        if (ce) xdiff10 <= ex_gt_xc9 ? ex9a - xc9
582
                                                                                : ex9a[EMSB+2] ? xc9 + (~ex9a+2'd1)
583
                                                                                : xc9 - ex9a;
584
 
585
// Determine which fraction to denormalize (the one with the
586
// smaller exponent is denormalized). If the exponents are equal
587
// denormalize the smaller fraction.
588
always @(posedge clk)
589
        if (ce) mfs <=
590
                xeq9 ? (a_gt_c9 ? {4'b0,fractc9,{FMSB+1{1'b0}}} : mo9)
591
                 : ex_gt_xc9 ? {4'b0,fractc9,{FMSB+1{1'b0}}} : mo9;
592
 
593
always @(posedge clk)
594
        if (ce) ops10 <= xeq9 ? (a_gt_c9 ? 1'b1 : 1'b0)
595
                                                                                                : (ex_gt_xc9 ? 1'b1 : 1'b0);
596
 
597
// -----------------------------------------------------------
598
// Clock #11
599
// Limit the size of the shifter to only bits needed.
600
// -----------------------------------------------------------
601
reg [7:0] xdif11;
602
 
603
always @(posedge clk)
604
        if (ce) xdif11 <= xdiff10 > FX+3 ? FX+3 : xdiff10;
605
 
606
// -----------------------------------------------------------
607
// Clock #12
608
// Determine the sticky bit
609
// -----------------------------------------------------------
610
 
611
wire sticky, sticky12;
612
wire [FX:0] mfs12;
613
wire [7:0] xdif12;
614
 
615
generate
616
begin
617
if (FPWID==128)
618
  redor128 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
619
else if (FPWID==96)
620
  redor96 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
621
else if (FPWID==84)
622
  redor84 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
623
else if (FPWID==80)
624
  redor80 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
625
else if (FPWID==64)
626
  redor64 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
627
else if (FPWID==32)
628
  redor32 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
629
else begin
630
        always @* begin
631
        $display("redor operation needed in fpFMA");
632
        $finish;
633
  end
634
end
635
end
636
endgenerate
637
 
638
// register inputs to shifter and shift
639
delay1 #(1)    u122(.clk(clk), .ce(ce), .i(sticky), .o(sticky12) );
640
delay1 #(8)    u123(.clk(clk), .ce(ce), .i(xdif11),   .o(xdif12) );
641
delay2 #(FX+1) u124(.clk(clk), .ce(ce), .i(mfs), .o(mfs12) );
642
 
643
// -----------------------------------------------------------
644
// Clock #13
645
// - denormalize operand (shift right)
646
// -----------------------------------------------------------
647
reg [FX+2:0] mfs13;
648
wire [FX:0] mo13;
649
wire ex_gt_xc13;
650
wire [FMSB+1:0] fractc13;
651
wire ops13;
652
 
653
delay4 #(FX+1) u131 (.clk(clk), .ce(ce), .i(mo9), .o(mo13));
654
delay4 u132 (.clk(clk), .ce(ce), .i(ex_gt_xc9), .o(ex_gt_xc13));
655
vtdl #(FMSB+2) u133 (.clk(clk), .ce(ce), .a(4'd3), .d(fractc9), .q(fractc13));
656
delay3 u134 (.clk(clk), .ce(ce), .i(ops10), .o(ops13));
657
 
658
always @(posedge clk)
659
        if (ce) mfs13 <= ({mfs12,2'b0} >> xdif12)|sticky12;
660
 
661
// -----------------------------------------------------------
662
// Clock #14
663
// Sort operands
664
// -----------------------------------------------------------
665
reg [FX+2:0] oa, ob;
666
wire a_gt_b14;
667
 
668
vtdl #(1) u141 (.clk(clk), .ce(ce), .a(4'd5), .d(a_gt_b8), .q(a_gt_b14));
669
 
670
always @(posedge clk)
671
        if (ce) oa <= ops13 ? {mo13,2'b00} : mfs13;
672
always @(posedge clk)
673
        if (ce) ob <= ops13 ? mfs13 : {fractc13,{FMSB+1{1'b0}},2'b00};
674
 
675
// -----------------------------------------------------------
676
// Clock #15
677
// - Sort operands
678
// -----------------------------------------------------------
679
reg [FX+2:0] oaa, obb;
680
wire realOp15;
681
wire [EMSB:0] ex15;
682
wire [EMSB:0] ex9c = ex9[EMSB+1] ? infXp : ex9[EMSB:0];
683
wire overflow15;
684
vtdl #(1) u151 (.clk(clk), .ce(ce), .a(4'd7), .d(realOp7), .q(realOp15));
685
vtdl #(EMSB+1) u152 (.clk(clk), .ce(ce), .a(4'd5), .d(ex9c), .q(ex15));
686
vtdl #(EMSB+1) u153 (.clk(clk), .ce(ce), .a(4'd5), .d(ex9[EMSB+1]| &ex9[EMSB:0]), .q(overflow15));
687
 
688
always @(posedge clk)
689
        if (ce) oaa <= a_gt_b14 ? oa : ob;
690
always @(posedge clk)
691
        if (ce) obb <= a_gt_b14 ? ob : oa;
692
 
693
// -----------------------------------------------------------
694
// Clock #16
695
// - perform add/subtract
696
// - addition can generate an extra bit, subtract can't go negative
697
// -----------------------------------------------------------
698
reg [FX+3:0] mab;
699
wire [FX:0] mo16;
700
wire [FMSB+1:0] fractc16;
701
wire Nan16;
702
wire cNan16;
703
wire aInf16, cInf16;
704
wire op16;
705
wire exinf16;
706
 
707
vtdl #(1) u161 (.clk(clk), .ce(ce), .a(4'd10), .d(qNaNOut5|aNan5|bNan5), .q(Nan16));
708
vtdl #(1) u162 (.clk(clk), .ce(ce), .a(4'd14), .d(cNan1), .q(cNan16));
709
vtdl #(1) u163 (.clk(clk), .ce(ce), .a(4'd9), .d(&ex6), .q(aInf16));
710
vtdl #(1) u164 (.clk(clk), .ce(ce), .a(4'd14), .d(cInf1), .q(cInf16));
711
vtdl #(1) u165 (.clk(clk), .ce(ce), .a(4'd14), .d(op1), .q(op16));
712
delay3 #(FX+1) u166 (.clk(clk), .ce(ce), .i(mo13), .o(mo16));
713
vtdl #(FMSB+2) u167 (.clk(clk), .ce(ce), .a(4'd6), .d(fractc9), .q(fractc16));
714
delay1 u169 (.clk(clk), .ce(ce), .i(&ex15), .o(exinf16));
715
 
716
always @(posedge clk)
717
        if (ce) mab <= realOp15 ? oaa - obb : oaa + obb;
718
 
719
// -----------------------------------------------------------
720
// Clock #17
721
// - adjust for Nans
722
// -----------------------------------------------------------
723
wire [EMSB:0] ex17;
724
reg [FX:0] mo17;
725
wire so17;
726
wire exinf17;
727
wire overflow17;
728
 
729
vtdl #(1)        u171 (.clk(clk), .ce(ce), .a(4'd7), .d(so9), .q(so17));
730
delay2 #(EMSB+1) u172 (.clk(clk), .ce(ce), .i(ex15), .o(ex17));
731
delay1 #(1) u173 (.clk(clk), .ce(ce), .i(exinf16), .o(exinf17));
732
delay2 u174 (.clk(clk), .ce(ce), .i(overflow15), .o(overflow17));
733
 
734
always @(posedge clk)
735
        casez({aInf16&cInf16,Nan16,cNan16,exinf16})
736
        4'b1???:        mo17 <= {1'b0,op16,{FMSB-1{1'b0}},op16,{FMSB{1'b0}}};   // inf +/- inf - generate QNaN on subtract, inf on add
737
        4'b01??:        mo17 <= {1'b0,mo16};
738
        4'b001?:        mo17 <= {1'b1,1'b1,fractc16[FMSB-1:0],{FMSB+1{1'b0}}};
739
        4'b0001:        mo17 <= 1'd0;
740
        default:        mo17 <= mab[FX+3:2];            // mab has two extra lead bits and two trailing bits
741
        endcase
742
 
743
assign o = {so17,ex17,mo17};
744
assign zero = {ex17,mo17}==1'd0;
745
assign inf = exinf17;
746
assign under = ex17==1'd0;
747
assign over = overflow17;
748
 
749
endmodule
750
 
751
 
752
// Multiplier with normalization and rounding.
753
 
754
module fpFMAnr(clk, ce, op, rm, a, b, c, o, inf, zero, overflow, underflow, inexact);
755
input clk;
756
input ce;
757
input op;
758
input [2:0] rm;
759
input  [MSB:0] a, b, c;
760
output [MSB:0] o;
761
output zero;
762
output inf;
763
output overflow;
764
output underflow;
765
output inexact;
766
 
767
wire [EX:0] fma_o;
768
wire fma_underflow;
769
wire fma_overflow;
770
wire norm_underflow;
771
wire norm_inexact;
772
wire sign_exe1, inf1, overflow1, underflow1;
773
wire [MSB+3:0] fpn0;
774
 
775
fpFMA #(FPWID) u1
776
(
777
        .clk(clk),
778
        .ce(ce),
779
        .op(op),
780
        .rm(rm),
781
        .a(a),
782
        .b(b),
783
        .c(c),
784
        .o(fma_o),
785
        .under(fma_underflow),
786
        .over(fma_overflow),
787
        .zero(),
788
        .inf()
789
);
790
fpNormalize #(FPWID) u2
791
(
792
        .clk(clk),
793
        .ce(ce),
794
        .i(fma_o),
795
        .o(fpn0),
796
        .under_i(fma_underflow),
797
        .under_o(norm_underflow),
798
        .inexact_o(norm_inexact)
799
);
800
fpRound         #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
801
fpDecomp        #(FPWID) u4(.i(o), .xz(), .vz(zero), .inf(inf));
802
vtdl                                            u5 (.clk(clk), .ce(ce), .a(4'd11), .d(fma_underflow), .q(underflow));
803
vtdl                                            u6 (.clk(clk), .ce(ce), .a(4'd11), .d(fma_overflow), .q(overflow));
804
delay3          #(1)    u7 (.clk(clk), .ce(ce), .i(norm_inexact), .o(inexact));
805
assign overflow = inf;
806
 
807
endmodule
808
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.